Dopingless Tunnel Research Articles

A novel Ge based overlapping gate dopingless tunnel FET with high performance

In this letter, the overlapping gate dopingless tunnel field-effect transistor (OGDL-TFET) is proposed and studied by TCAD simulation. To increase the tunneling efficiency and reduce the manufacture difficulty, a dopingless germanium tunneling junction based on charge plasma concept is induced in OGDL-TFET. A high efficiency line tunneling junction is formed by the gate/backgate overlap. The on-state current of 75.5 μA μm−1 and subthreshold swing of 1.9 mV/dec can be obtained. With cut-off frequency of 16.53 GHz and gain bandwidth product of 2.44 GHz, OGDL-TFET obtains good analog and radio frequency performance. The considerable good performance makes OGDL-TFET very attractive for ultra-low power application.

Design and Analog Performance Analysis of Triple Material Gate Based Doping-Less Tunnel Field Effect Transistor

Design and Analog Performance Analysis of Triple Material Gate Based Doping-Less Tunnel Field Effect Transistor

An In0.53Ga0.47As/In0.52Al0.48As Heterojunction Dopingless Tunnel FET With a Heterogate Dielectric for High Performance

In this paper, an In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.48</sub> As heterojunction dopingless tunnel field-effect transistor (HDL-TFET) with an HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> heterogate dielectric is proposed, where the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -pocket with variable electron concentration can be formed by adjusting the length of source-side channel (LSC) based on the charge plasma concept, instead of employing conventional ion implantation or dual-material gate techniques. It aims to improve the device performance and simplify the device fabrication. At the drain bias of 0.3 V, numerical simulations show that the on-state current (ION) of the HDL-TFET with LSC = 4 nm can approach ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> A/μm that is far higher than that of the Si-DL-TFET (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/μm), and the average subthreshold swing (SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> ) can approach 36.6 mV/decade that is significantly lower than that of the Si-DL-TFET (89.2 mV/decade). It is also found that the drain-induced barrier lowering (DIBL) effect and the ambipolar current can be effectively suppressed in the HDL-TFET because of an existence of heterojunction. Under the condition of low gate and drain biases, the HDL-TFET exhibits peak values of the cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and the maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) approaching 13 and 4.73 GHz, respectively, while the Si-DL-TFET yields those of 8.05 and 2.26 GHz, respectively, under relatively higher biases. It indicates that the HDL-TFET is a promising device for low-power consumption radio frequency applications.

Design and Investigation of the High Performance Doping-Less TFET with Ge/Si0.6Ge0.4/Si Heterojunction

A high performance doping-less tunneling field effect transistor with Ge/Si0.6Ge0.4/Si heterojunction (H-DLTFET) is proposed in this paper. Compared to the conventional doping-less tunneling field effect transistor (DLTFET), the source and channel regions of H-DLTFET respectively use the germanium and Si0.6Ge0.4 materials to get the steeper energy band, which can also increase the electric field of source/channel tunneling junction. Meanwhile, the double-gate process is used to improve the gate-to-channel control. In addition, the effects of Ge content, electrode work functions, and device structure parameters on the performance of H-DLTFET are researched in detail, and then the above optimal device structure parameters can be obtained. Compared to the DLTFET, the simulation results show that the maximum on-state current, trans-conductance, and output current of H-DLTFET are all increased by one order of magnitude, whereas the off-state current is reduced by two orders of magnitude, so the switching ratio increase by three orders of magnitude. At the same time, the cut-off frequency and gain bandwidth product of H-DLTFET increase from 1.75 GHz and 0.23 GHz to 23.6 GHz and 4.69 GHz, respectively. Therefore, the H-DLTFET is more suitable for the ultra-low power integrated circuits.

Design and Performance Analysis of Dielectrically Modulated Doping-Less Tunnel FET-Based Label Free Biosensor

In this paper, we have proposed a charge plasma-based doping less double gated tunnel FET (DLDGTFET)-based biosensor using dielectric modulation with a cavity introduced at the source side for the label free sensing of the biomolecules. These biomolecules are immobilized in the cavity region to induce drain current. The sensing of the biomolecules is based on the drain current of the device while the drain current is based on the dielectric constant and the interfacing charges of the biomolecules. The cavity length is varied between 25 and 30 nm and different dielectric constants have been used. The expansion of the cavity length results in slight reduction of the drain current due to lowering of the capacitance. Higher dielectric constants result in better drain current values which leads to an increase in the sensitivity of the device. The maximum sensitivity attained was as high as $1.0\times 10^{10}$ . As compared to other transistors, DLDGTFET provides better sensitivity as a biosensor and also the leakage current is low.

A Doping-Less Tunnel Field-Effect Transistor with Si0.6Ge0.4 Heterojunction for the Improvement of the On–Off Current Ratio and Analog/RF Performance

In this paper, a novel doping-less tunneling field-effect transistor with Si0.6Ge0.4 heterojunction (H-DLTFET) is proposed using TCAD simulation. Unlike conventional doping-less tunneling field-effect transistors (DLTFETs), in H-DLTFETs, germanium and Si0.6Ge0.4 are used as source and channel materials, respectively, to provide higher carrier mobility and smaller tunneling barrier width. The energy band and charge carrier tunneling efficiency of the tunneling junction become steeper and higher as a result of the Si0.6Ge0.4 heterojunction. In addition, the effects of the source work function, gate oxide dielectric thickness, and germanium content on the performance of the H-DLTFET are analyzed systematically, and the below optimal device parameters are obtained. The simulation results show that the performance parameters of the H-DLTFET, such as the on-state current, on/off current ratio, output current, subthreshold swing, total gate capacitance, cutoff frequency, and gain bandwidth (GBW) product when Vd = 1 V and Vg = 2 V, are better than those of conventional silicon-based DLTFETs. Therefore, the H-DLTFET has better potential for use in ultra-low power devices.

Design and investigation of dopingless dual-gate tunneling transistor based on line tunneling

The dopingless tunneling FET (DLTFET) has attracted more and more attention due to the reduction of process complexity comparing to traditional TFET with heavy doping source and drain regions. But the on-state current of conventional DLTFET is lower because its on-state current is only determined by point tunneling (PT) between source and channel. In this work, a new dual-gate DLTFET based on line tunneling (LT) is designed and studied by Sentaurus TCAD simulation tool. The on-state current and subthreshold swing (SS) of DLTFET are greatly improved by skillfully designing back gate engineering and bias. Applying this novel design, the line tunneling is created from channel bottom to channel top, which dramatically enhances tunneling area and tunneling current. So the on-state current of LT_DLTFET consists of point tunneling between source and channel as well as line tunneling in channel region. Comparing to the traditional PT_DLTFET based on Ge, the simulation results reveal that the on-state current of LT_DLTFET based on Ge is increased to 14.8μA/μm from 6.5μA/μm at Vg=1V and Vd=0.5V, and the average SS and minimum SS are decreased to 22.9mV/dec and 6.5mV/dec from 33.9 mV/dec and 9.5mV/dec, respectively. The LT_DLTFET is also proper to both Si and III-V materials. This design greatly promotes the application potential of DLTFET.

Dopingless Tunnel Field-Effect Transistor With Oversized Back Gate: Proposal and Investigation

Tunnel field-effect transistors (TFETs) have shown attractive device performance making them a potential candidate to replace MOSFETs in future technologies. However, the inherent ambipolar characteristic of TFETs poses challenge in digital applications. The gate–drain overlap in conventional TFETs efficiently suppresses the ambipolar conductivity. On the other hand, in dopingless TFETs (DLTFETs), due to the requirement of separate gate and drain electrodes for electrostatically creating doped and intrinsic regions, gate–drain overlap cannot be realized. However, gate–drain overlap can be effectively realized using oversized back gate (OBG). Therefore, in this paper, we have proposed a DLTFET with an OBG that effectively suppresses ambipolar behavior even upto gate voltage ${V}_{\textsf {GS}} = -\textsf {1}$ V. Misalignment study is also performed for the gate length ${L}_{G} = \textsf {20}$ nm which has been reported to degrade the tunneling phenomenon at gate–source interface. It is observed that the proposed device is more tolerant to misalignment due to its OBG. The OBG also provides improvement in ${I}_{\textsf {on}}$ ( $\sim 1.4\times $ ) due to enhanced band bending at gate–source interface. To demonstrate the advantage of proposed device architecture over existing architectures, we compare the performance of proposed device with other existing techniques such as dual material gate and dual material drain architectures. The OBG-DLTFET has shown better ambipolar and on-state characteristics in comparison to the existing techniques.

Electrostatically doped tunnel CNTFET model for low-power VLSI circuit design

With advantages such as low sub-threshold swing, low OFF-state current and the ability to attain a higher ON–OFF ratio, the tunnel CNTFET is one of the most comprehensively investigated devices for low-power application. The problems associated with this device are fabrication issues since conventional doping is not possible in CNTs. Therefore, a doping-less tunnel CNTFET is proposed which is free from problems associated with a conventional tunnel CNTFET. A mathematical model is developed for an electrostatically doped tunnel CNTFET, and to validate the model accuracy and the equation set, the simulation results are compared with NanoTCAD ViDES results. Finally, the developed model is deployed in an inverter design to verify the suitability of the model for circuit applications.

Study of metal strip insertion and its optimization in doping less TFET

In this manuscript, a novel structure for dopingless tunnel field effect transistor (DL TFET) is introduced which comprises of metal strip (MS) in the oxide region near source/channel junction. Gate and drain work function engineering with hetero gate dielectric is used in this device which enhances the ON-state current, reduces the ambipolarity and also improves the RF performance. The increment in ON-state current with high subthreshold swing is achieved by the effect of MS. Steeper tunneling junction is achieved with the help of aforementioned modifications at the S/C junction. In this way, we increase the rate of tunneling at this interface and because of this, the threshold voltage of the proposed device reduces drastically. Further, study of ambipolarity suppression is done by using underlap of gate electrode near drain/channel (D/C) interface. Furthermore, temperature variation effect also incorporated in this manuscript, where study related to the threshold voltage and ON-state current is analysed by TCAD simulation. Moreover, most optimized MS length and work function are concluded in this paper for all simulations. Optimization for MS length and workfunction is analysed using TCAD simulation tool and shown in tabular form with one table showing effect of different work functions of MS on threshold voltage, ON-state current and SS, whereas another table shows the effect of MS length variations on RF parameters.

Impact of interface trap charges on dopingless tunnel FET for enhancement of linearity characteristics

For the first time, we have explored the effect of positive and negative interface trap charges on the dopingless device using charge plasma concept and named the proposed device as heterogeneous gate dielectric charge plasma tunnel field-effect transistor (HD-CP-TFET). The heterogeneous gate dielectric is considered to improve the ON-state current and device performance. The main intention of this work is to improve the drain current, transconductance characteristics along with linearity figure-of-merits (FOMs). A comparative analysis is done with conventional CP-TFET in the presence of interface trap charges (ITCs). From comparative results, it is found that the proposed device shows a better performance in the presence of interface trap charges. All the simulations are performed on ATLAS TCAD device simulator. The results show that the proposed device has a better tunneling current, transconductance (\(g_{\text {m}}\)), cut-off frequency (\(f_{\text {T}}\)), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3). Thus, the proposed device (HD-CP-TFET) shows the better performance in the presence of interface trap charges and indicates that this device is suitable for low-voltage analog/RF applications.

Hetero-Material Gate Doping-Less Tunnel FET and Its Misalignment Effects on Analog/RF Parameters

In this paper, with the use of a hetero-material gate technique, a tunnel field-effect transistor (TFET) subject to charge plasma technique is proposed, named as hetero-material gate doping-less tunnel FET (HMG-DLTFET) and a brief study has been done on the effects due to misalignment of the bottom gate towards drain (GMAD) and towards source (GMAS). The proposed devices provide better performance as the drive current increased by three times as compared to conventional doping-less TFET (DLTFET). The results are then analyzed and compared with conventional doped hetero-material gate double-gate tunnel FET (HMG-DGTFET). The analog/radiofrequency (RF) performance has been studied for both devices and comparative analysis has been done for different parameters such as drain current (ID), transconductance (gm), output conductance (gd), total gate capacitance (Cgg) and cutoff frequency (fT). Both devices performed similarly in different misalignment configurations. When the bottom gate is perfectly aligned, the best performance is observed for both devices, but the doping-less device gives slightly more freedom for fabrication engineers as the amount of tolerance for HMG-DLTFET is better than that of HMG-DGTFET.

A High-Performance Gate Engineered InGaN Dopingless Tunnel FET

A gate engineered InGaN dopingless tunnel FET (DL-TFET) using the charge plasma concept is proposed and investigated by silvaco Atlas simulation. In0.75Ga0.25N is a direct gap semiconductor, and the effective tunneling mass of electron and hole is smaller than that of silicon, which induces that the drain current and average subthreshold swing (SSavg) of InGaN DL-TFET improve $\text {1.3}\times \text {10}^{\text {2}}$ times and 51.1% than that of Si DL-TFET at the overdrive voltage of 0.5 V, respectively. What is more, better device performances are achieved by gate engineering with appropriate “In” fraction, proper space between the gate and source ( ${L}_{\text {gs}}$ ), and appropriate tunneling gate work function ( $\Phi _{\text {TG}}$ ). The direct-current, RF, and energy-efficient performance studies show that SSavg of 7.9 mV/dec, an on-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $\text {8.02} \times \text {10}^{-\text {5}}$ A/ $\mu \text{m}$ , a cutoff frequency ( ${f}_{T}$ ) of 119 GHz, and an energy delay product of 0.64 fJ-ps/ $\mu \text{m}$ can be obtained in the proposed TFET. This paper indicates that the gate engineered InGaN DL-TFET is a promising TFET for low-power RF and digital logic applications.

Gate misalignment effects on analog/RF performance of charge plasma-based doping-less tunnel FET

In this paper, gate misalignment effect on charge plasma-based doping-less tunnel FET (DLTFET) is demonstrated for the first time. The effects of bottom gate misalignment on either towards source (GMAS) or towards drain (GMAD) are then compared with the conventional doped TFET (DGTFET). This paper also discusses the effect of misalignment on the bases of different analog/RF parameters such as transconductance (gm), output conductance (gd), intrinsic gain (AV), total gate capacitance (Cgg), and cut-off frequency (fT). When bottom gate is misaligned towards source, DLTFET provides a better performance than DGTFET and shows the best results when the device is 50% misaligned. While gate misalignment towards drain, both devices show similar performance and degrade with the increase in misalignment. The DLTFET is found to have a better tolerance to the different misalignment configurations than DGTFET.

A New Design Approach of Dopingless Tunnel FET for Enhancement of Device Characteristics

Formation of abrupt tunneling junction for the sub-nanometer tunnel FET (TFET) is crucial for achieving better electrical behavior. This task is more challenging in the case of dopingless TFETs (DL TFETs). In this concern, we propose a novel design of DL TFET, wherein a metallic layer has been placed in the oxide region at the space present between gate and source electrode (used for inducing p+ region) of conventional dopingless n-TFET to overcome the issue of low on-state current ( $\text{I}_{\mathrm{on}}$ ) due to presence of tunneling barrier. Proposed modification is helpful for achieving steeper tunneling junction at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface. The optimization for work function of the metal layer (ML) has been performed for improving $\text {I}_{\mathrm{on}}$ , point subthreshold swing and threshold voltage ( $\text {V}_{\text {th}}$ ). Finally, the impact of the ML misalignment from the gate/source terminal and optimization of its length is also presented.

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET (HD_DMG_DLTFET). It is compared with conventional doping-less TFET (DLTFET) and dual material gate doping-less TFET (DMG_DLTFET) on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current (), , and average subthreshold slope (). The proposed device offers low total gate capacitance (Cgg) along with higher drive current. However, with a better transconductance (gm) and cut-off frequency (fT), the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage (VEA) and output conductance (gd) are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices. From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

Influence of Germanium source on dopingless tunnel-FET for improved analog/RF performance

Dopingless (DL) and junctionless devices have attracted attention due to their simplified fabrication process and low thermal budget requirements. Therefore, in this work, we investigated the influence of low band gap Germanium (Ge) instead of Silicon (Si) as a “Source region” material in dopingless (DL) tunnel field-effect transistor (DLTFET). We observed that the Ge source DLTFET delivers much better performance in comparison to Si DLTFET under various analog/RF figure of merits (FOMs), such as transconductance (gm), transconductance generation factor (TGF) (gm/Id), output conductance (gd), output resistance (RO), intrinsic gain (gmRO), intrinsic gate delay (τ) and RF FOMs, like unity gain frequency (fT), gain bandwidth product (GBW) along with various gate capacitances. These parameters were extracted using 2D TCAD device simulations through small signal ac analysis. Higher ION/IOFF ratio (1014) of Ge source DLTFET can reduce the dynamic as well as static power in digital circuits, while higher transconductance generation factor (gm/Id) ∼ 2287 V−1 can lower the bias power of an amplifier. Similarly, enhanced RF FOMs i.e unity gain frequency (fT) and gain bandwidth product (GBW) in Gigahertz range projects the proposed device preference for RF circuits.

Analog and RF performance of doping-less tunnel FETs with $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$ Si 0.55 Ge 0.45 source

This paper reports studies of a doping-less tunnel field-effect transistor (TFET) with a $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$Si0.55Ge0.45 source structure aimed at improving the performance of charge-plasma-based doping-less TFETs. The proposed device achieves an improved ON-state current ($$I_{{\mathrm{ON}}} \sim {4.88} \times {10}^{-5}\,{\mathrm{A}}/\upmu {\mathrm{m}}$$ION~4.88×10-5A/μm), an $$I_\mathrm{ON}/I_\mathrm{OFF}$$ION/IOFF ratio of $${6.91} \times {10}^{12}$$6.91×1012, an average subthreshold slope ($$\hbox {AV-SS}$$AV-SS) of $$\sim $$~$${64.79}\,{\mathrm{mV/dec}}$$64.79mV/dec, and a point subthreshold slope (SS) of 14.95 mV/dec. This paper compares the analog and radio of frequency (RF) parameters of this device with those of a conventional doping-less TFET (DLTFET), including the transconductance ($$g_{{\mathrm{m}}}$$gm), transconductance-to-drain-current ratio $$(g_\mathrm{m}/I_\mathrm{D})$$(gm/ID), output conductance $$(g_\mathrm{d})$$(gd), intrinsic gain ($$A_{{\mathrm{V}}}$$AV), early voltage ($$V_{{\mathrm{EA}}}$$VEA), total gate capacitance ($$ C_{{\mathrm{gg}}}$$Cgg), and unity-gain frequency ($$f_{{\mathrm{T}}}$$fT). Based on the simulated results, the $$\hbox {Si}_{0.55}\hbox {Ge}_{0.45}$$Si0.55Ge0.45-source DLTFET is found to offer superior analog as well as RF performance.

Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform

In this paper for the first time, InAs based doping-less Tunnel FET is proposed and investigated. This paper also demonstrates and discusses the impact of gate stacking (SiO2 + HfO2) with equivalent oxide thickness EOT = 0.8 for analog/RF performance. The charge plasma technique is used to form source/drain region on an intrinsic InAs body by selecting proper work function of metal electrode. The paper compares different combinations of gate stacking (SiO2 and HfO2) on the basis of different analog and RF parameters such as transconductance (gm), transconductance to drive current ratio (gm/ID), output conductance (gd), intrinsic gain (AV), total gate capacitance (Cgg) and unity-gain cutoff frequency (fT). The proposed device produces an ON state current of ION ∼6 mA along with ION/IOFF ∼1012, point subthreshold slope (SS ∼ 1.9 mV/dec), average subthreshold slope (AV-SS ∼ 14.2 mV/dec) and cut-off frequency in Terahertz. The focus of this work is to eliminate the fabrication issues and providing the enhanced performance compared to doped device.

Performance analysis of charge plasma based dual electrode tunnel FET

This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDLTEFT gives the superior results with high ON state current (ION ∼ 0.56 mA/μm), ION/IOFF ratio ∼ 9.12 × 1013 and an average subthreshold swing (AV-SS ∼ 48 mV/dec). The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.