Dopingless TFET Research Articles

Comparative study of InGaN and InGaAs based dopingless TFET with different gate engineering techniques

In this paper, we have presented the comparative analysis of InGaN and InGaAs based DL TFETs with different gate engineering methods for lowering the sub-threshold swing and increasing the ION/IOFF ratio. The 2D simulation study is carried out for comparing the results of conventional DL TFET with three gate engineered structures. InGaAs doped hetero-dielectric hetero-gate DL TFET shows best result of about ~2.217 times increase in the ION/IOFF, 40.17% decrease in the average sub-threshold swing as compared to their respective DL TFET structure. Similarly, InGaN doped HD-HG DL TFET shows ~8.514 times increase in the ION/IOFF, 45.83% decrease in the average sub-threshold swing as compared to their respective DL TFET structure. Finally the result shows InGaAs based HD-HG DL TFET as a favourable device for low power and digital applications.

Design and Analog Performance Analysis of Triple Material Gate Based Doping-Less Tunnel Field Effect Transistor

Design and Analog Performance Analysis of Triple Material Gate Based Doping-Less Tunnel Field Effect Transistor

An In0.53Ga0.47As/In0.52Al0.48As Heterojunction Dopingless Tunnel FET With a Heterogate Dielectric for High Performance

In this paper, an In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.48</sub> As heterojunction dopingless tunnel field-effect transistor (HDL-TFET) with an HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> heterogate dielectric is proposed, where the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -pocket with variable electron concentration can be formed by adjusting the length of source-side channel (LSC) based on the charge plasma concept, instead of employing conventional ion implantation or dual-material gate techniques. It aims to improve the device performance and simplify the device fabrication. At the drain bias of 0.3 V, numerical simulations show that the on-state current (ION) of the HDL-TFET with LSC = 4 nm can approach ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> A/μm that is far higher than that of the Si-DL-TFET (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/μm), and the average subthreshold swing (SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> ) can approach 36.6 mV/decade that is significantly lower than that of the Si-DL-TFET (89.2 mV/decade). It is also found that the drain-induced barrier lowering (DIBL) effect and the ambipolar current can be effectively suppressed in the HDL-TFET because of an existence of heterojunction. Under the condition of low gate and drain biases, the HDL-TFET exhibits peak values of the cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and the maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) approaching 13 and 4.73 GHz, respectively, while the Si-DL-TFET yields those of 8.05 and 2.26 GHz, respectively, under relatively higher biases. It indicates that the HDL-TFET is a promising device for low-power consumption radio frequency applications.

Design and Investigation of the High Performance Doping-Less TFET with Ge/Si0.6Ge0.4/Si Heterojunction

A high performance doping-less tunneling field effect transistor with Ge/Si0.6Ge0.4/Si heterojunction (H-DLTFET) is proposed in this paper. Compared to the conventional doping-less tunneling field effect transistor (DLTFET), the source and channel regions of H-DLTFET respectively use the germanium and Si0.6Ge0.4 materials to get the steeper energy band, which can also increase the electric field of source/channel tunneling junction. Meanwhile, the double-gate process is used to improve the gate-to-channel control. In addition, the effects of Ge content, electrode work functions, and device structure parameters on the performance of H-DLTFET are researched in detail, and then the above optimal device structure parameters can be obtained. Compared to the DLTFET, the simulation results show that the maximum on-state current, trans-conductance, and output current of H-DLTFET are all increased by one order of magnitude, whereas the off-state current is reduced by two orders of magnitude, so the switching ratio increase by three orders of magnitude. At the same time, the cut-off frequency and gain bandwidth product of H-DLTFET increase from 1.75 GHz and 0.23 GHz to 23.6 GHz and 4.69 GHz, respectively. Therefore, the H-DLTFET is more suitable for the ultra-low power integrated circuits.

A Doping-Less Tunnel Field-Effect Transistor with Si0.6Ge0.4 Heterojunction for the Improvement of the On–Off Current Ratio and Analog/RF Performance

In this paper, a novel doping-less tunneling field-effect transistor with Si0.6Ge0.4 heterojunction (H-DLTFET) is proposed using TCAD simulation. Unlike conventional doping-less tunneling field-effect transistors (DLTFETs), in H-DLTFETs, germanium and Si0.6Ge0.4 are used as source and channel materials, respectively, to provide higher carrier mobility and smaller tunneling barrier width. The energy band and charge carrier tunneling efficiency of the tunneling junction become steeper and higher as a result of the Si0.6Ge0.4 heterojunction. In addition, the effects of the source work function, gate oxide dielectric thickness, and germanium content on the performance of the H-DLTFET are analyzed systematically, and the below optimal device parameters are obtained. The simulation results show that the performance parameters of the H-DLTFET, such as the on-state current, on/off current ratio, output current, subthreshold swing, total gate capacitance, cutoff frequency, and gain bandwidth (GBW) product when Vd = 1 V and Vg = 2 V, are better than those of conventional silicon-based DLTFETs. Therefore, the H-DLTFET has better potential for use in ultra-low power devices.

Controlling ambipolar current of dopingless tunnel field-effect transistor

Ambipolarity in tunnel field-effect transistor (TFET) is a subject of grave concern in the current scenario of the semiconductor industry as this property of device limits its usability in CMOS circuit applications. In this concern, this paper presents a new approach to suppress the ambipolar behavior of dopingless TFET (DL TFET) by controlling the lateral band-to-band tunneling at the drain/channel interface. To execute this, a metal strip is embedded inside the oxide region between gate and drain terminals to modulate the energy bands for preventing the tunneling of charge carriers. The energy bands are widened at the drain-channel junction using this technique and correspondingly ambipolarity is reduced by a factor of $$10^{11}$$ . The variation in the energy bands is examined under different negative gate bias for the proposed device and conventional device which has shown that the energy barrier for the proposed device remains wider for different voltages under the influence of metal embedded. Alignment of the metal strip is varied to obtain the desired performance of the device. In this regard, optimization of work function and length of metal strip along with its position is demonstrated considering its impact on the ambipolar current and ON-state current, which gave 4.0 eV work function and 20 nm as the optimized work function and length of the metal strip, respectively.

Effective design technique for improvement of electrostatics behaviour of dopingless TFET: proposal, investigation and optimisation

Rapid tunnelling junction formation is a much crucial issue with conventional sub-nanometre tunnel field-effect transistor (TFET) to obtain improved electrostatics characteristics. This task becomes more problematic and complicated for dopingless TFET as a result of wide tunnelling barrier at channel/source junction. In this regard, a new approach has been employed by implanting the metal angle (MA) inside the dielectric layer near channel/source joint to obtain enhanced electrical behaviour of the proposed structure. Employment of MA of small work-function increases electron density at channel/source interface to have improved electron tunnelling rate. Work-function optimisation of MA on RF/DC parameters is analysed in device optimisation part of this work. Simultaneously length optimisation of MA is also presented in the device optimisation section to ease the complex fabrication steps. In addition to these, circuit level performance of proposed and conventional structures is also analysed in this study.

Dopingless Tunnel Field-Effect Transistor With Oversized Back Gate: Proposal and Investigation

Tunnel field-effect transistors (TFETs) have shown attractive device performance making them a potential candidate to replace MOSFETs in future technologies. However, the inherent ambipolar characteristic of TFETs poses challenge in digital applications. The gate–drain overlap in conventional TFETs efficiently suppresses the ambipolar conductivity. On the other hand, in dopingless TFETs (DLTFETs), due to the requirement of separate gate and drain electrodes for electrostatically creating doped and intrinsic regions, gate–drain overlap cannot be realized. However, gate–drain overlap can be effectively realized using oversized back gate (OBG). Therefore, in this paper, we have proposed a DLTFET with an OBG that effectively suppresses ambipolar behavior even upto gate voltage ${V}_{\textsf {GS}} = -\textsf {1}$ V. Misalignment study is also performed for the gate length ${L}_{G} = \textsf {20}$ nm which has been reported to degrade the tunneling phenomenon at gate–source interface. It is observed that the proposed device is more tolerant to misalignment due to its OBG. The OBG also provides improvement in ${I}_{\textsf {on}}$ ( $\sim 1.4\times $ ) due to enhanced band bending at gate–source interface. To demonstrate the advantage of proposed device architecture over existing architectures, we compare the performance of proposed device with other existing techniques such as dual material gate and dual material drain architectures. The OBG-DLTFET has shown better ambipolar and on-state characteristics in comparison to the existing techniques.

Effective approach to enhance DC and high‐frequency performance of electrically doped TFET

The need to overcome the shortcomings of conventional tunnel field-effect transistor (TFET) has driven many to come up with advanced TFET innovations. This Letter presents a comparative analysis of new techniques to enhance DC/radio-frequency (RF) performance of dopingless TFETs. In this regard, two advanced structures have been compared along with conventional electrically doped TFET. The devices – electrically doped TFET, low work-function strip electrically doped TFET and low work-function live strip electrically doped TFET are investigated in terms of DC, RF and linearity. This Letter focuses on electrical doping on dopingless substrate to reduce random dopant fluctuations and fabrication complications. The comparative analysis illustrates the importance of low work-function live strip (LWLS) over low work-function strip (LWS). In addition, an optimisation of length and position of LWS and LWLS is also investigated for providing fabrication ease.

Impact of Spacer-Gate Engineered Workfunction on the Performance of Dopingless TFET

Impact of Spacer-Gate Engineered Workfunction on the Performance of Dopingless TFET

Study of metal strip insertion and its optimization in doping less TFET

In this manuscript, a novel structure for dopingless tunnel field effect transistor (DL TFET) is introduced which comprises of metal strip (MS) in the oxide region near source/channel junction. Gate and drain work function engineering with hetero gate dielectric is used in this device which enhances the ON-state current, reduces the ambipolarity and also improves the RF performance. The increment in ON-state current with high subthreshold swing is achieved by the effect of MS. Steeper tunneling junction is achieved with the help of aforementioned modifications at the S/C junction. In this way, we increase the rate of tunneling at this interface and because of this, the threshold voltage of the proposed device reduces drastically. Further, study of ambipolarity suppression is done by using underlap of gate electrode near drain/channel (D/C) interface. Furthermore, temperature variation effect also incorporated in this manuscript, where study related to the threshold voltage and ON-state current is analysed by TCAD simulation. Moreover, most optimized MS length and work function are concluded in this paper for all simulations. Optimization for MS length and workfunction is analysed using TCAD simulation tool and shown in tabular form with one table showing effect of different work functions of MS on threshold voltage, ON-state current and SS, whereas another table shows the effect of MS length variations on RF parameters.

Hetero-Material Gate Doping-Less Tunnel FET and Its Misalignment Effects on Analog/RF Parameters

In this paper, with the use of a hetero-material gate technique, a tunnel field-effect transistor (TFET) subject to charge plasma technique is proposed, named as hetero-material gate doping-less tunnel FET (HMG-DLTFET) and a brief study has been done on the effects due to misalignment of the bottom gate towards drain (GMAD) and towards source (GMAS). The proposed devices provide better performance as the drive current increased by three times as compared to conventional doping-less TFET (DLTFET). The results are then analyzed and compared with conventional doped hetero-material gate double-gate tunnel FET (HMG-DGTFET). The analog/radiofrequency (RF) performance has been studied for both devices and comparative analysis has been done for different parameters such as drain current (ID), transconductance (gm), output conductance (gd), total gate capacitance (Cgg) and cutoff frequency (fT). Both devices performed similarly in different misalignment configurations. When the bottom gate is perfectly aligned, the best performance is observed for both devices, but the doping-less device gives slightly more freedom for fabrication engineers as the amount of tolerance for HMG-DLTFET is better than that of HMG-DGTFET.

Impact of asymmetric dual-k spacers on tunnel field effect transistors

In this paper, we propose a novel device structure for tunneling FETs, based on charge plasma concept, such as junctionless-TFET (JLTFET) and dopingless-TFET (DLTFET) with asymmetric dual-k spacer. Using 2-D simulations, we demonstrate that ON-state current increases significantly with the use of asymmetric dual-k spacers between the gate and p-gate/source in JLTFET and DLTFET. We optimize the spacer length ( $$L_\mathrm{S}$$ ) between gate and p-gate/source for these transistors having low-k spacer only. We have employed dual-k spacer, which consists of high-k spacer on gate side and low-k spacer on source side, which could also be interchangeably used. We also optimize the inner high-k spacer length for better analog and digital performance and investigate their impacts on the transistor performance. The simulation results for asymmetric dual-k spacers JLTFET (ADK-JLTFET) offer an improvement of two orders in ON-state current, with point subthreshold slope of 40 mV/dec, and a high $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ratio of $$\sim 10^{8}$$ . We estimate the improvement in digital performance using ‘ $$I_{\mathrm{o}}/C_{\mathrm{in}}$$ ’ ( $$I_{\mathrm{D}}/C_{\mathrm{GG}}$$ ) and analog performance using unity gain frequency ‘ $$f_{\mathrm{T}}$$ ’ as the figure of merit. We observe that the proposed ADK-JLTFET offers 30 times increase in $$I_{\mathrm{o}}/C_{\mathrm{in}}$$ and 24 times increase in $$f_{\mathrm{T}}$$ as compared to JLTFET with only low-k spacer. Due to similar working mechanism, ADK-DLTFET also shows similar improvements.

A new design approach for enhancement of DC/RF performance with improved ambipolar conduction of dopingless TFET

In this article, we propose a new device structure to suppress ambipolar conduction with improved DC/RF performance of dopingless TFET (DL-TFET). Here gate underlapping technique is applied near drain side to suppress ambipolarity, which results improved Analog/RF performance of the device. In addition to gate underlapping technique, a novel initiative has also been taken by placing a metal angle (MA) in the oxide layer near source/channel interface to get excellent DC characteristics of the proposed device. Placement of MA is helpful to increase abruptness at source/channel interface for higher tunneling rate of charge carriers. Length variation of gate underlapping has been performed in the section of device optimization for reducing ambipolarity of the device. Simultaneously, variation in workfunction and position of metal angle is also analysed in this section to ease the fabrication complexity.

Dual metal drain Ge‐source dopingless TFET with enhanced turn‐ON steep subthreshold swing and high ON‐current

A novel dopingless Ge-source dual metal drain double gate tunnel field effect transistor is presented with the help of work function engineering. Proposed device makes use of the dopingless concept, charge plasma for carrier doping concentration below the drain/source region that permits dynamic configuration by choosing suitable work function for drain/source metal electrode. In the proposed device, the n + drain region is divided into two parts of low and high work function. The work function of the metal nearest to the drain–channel junction is relatively higher than the other metal for creating a potential barrier for restricting the tunnelling of holes when the negative gate voltage is applied. By using low energy bandgap Ge material, the tunnelling probability and drive current of the device are increased. The proposed device offers high I ON/I OFF ratio (∼1013), smaller point subthreshold swing (SS) (∼31 mV/decade), average SS (∼43 mV/decade).

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS≤60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET (HD_DMG_DLTFET). It is compared with conventional doping-less TFET (DLTFET) and dual material gate doping-less TFET (DMG_DLTFET) on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current (), , and average subthreshold slope (). The proposed device offers low total gate capacitance (Cgg) along with higher drive current. However, with a better transconductance (gm) and cut-off frequency (fT), the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage (VEA) and output conductance (gd) are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices. From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

Influence of Germanium source on dopingless tunnel-FET for improved analog/RF performance

Dopingless (DL) and junctionless devices have attracted attention due to their simplified fabrication process and low thermal budget requirements. Therefore, in this work, we investigated the influence of low band gap Germanium (Ge) instead of Silicon (Si) as a “Source region” material in dopingless (DL) tunnel field-effect transistor (DLTFET). We observed that the Ge source DLTFET delivers much better performance in comparison to Si DLTFET under various analog/RF figure of merits (FOMs), such as transconductance (gm), transconductance generation factor (TGF) (gm/Id), output conductance (gd), output resistance (RO), intrinsic gain (gmRO), intrinsic gate delay (τ) and RF FOMs, like unity gain frequency (fT), gain bandwidth product (GBW) along with various gate capacitances. These parameters were extracted using 2D TCAD device simulations through small signal ac analysis. Higher ION/IOFF ratio (1014) of Ge source DLTFET can reduce the dynamic as well as static power in digital circuits, while higher transconductance generation factor (gm/Id) ∼ 2287 V−1 can lower the bias power of an amplifier. Similarly, enhanced RF FOMs i.e unity gain frequency (fT) and gain bandwidth product (GBW) in Gigahertz range projects the proposed device preference for RF circuits.

Pressure sensor based on MEMS nano-cantilever beam structure as a heterodielectric gate electrode of dopingless TFET

Micro-electromechanical systems (MEMS) technology has enticed numerous scientists since recent decades particularly in the field of miniaturized-sensors and actuators. Pressure sensor is pivotal component in both of the forerunning fields. The pursuance of a pressure sensor is exigently relying upon its different physical properties i.e. Piezo-resistive, Piezoelectric, Capacitive, Magnetic and Electrostatic. This article presents an outline and scrutiny of the Doping-less Cantilever Based Pressure Sensor using tunnel field effect transistor technology. The propounded pressure sensor based on the principle of capacitive gate coupling, due to which the tunneling current is modified. Additionally, to enhance the affectability of pressure sensor, the work function of metal gate electrode is amended using gas molecule diffusion. Simulation uncovers a phenomenal relationship amongst hypothetical and practical accepts of configuration. The pressure sensor is composed at Silvaco Atlas tool utilizing 40 nm technologies. The performance results exhibit that the proposed model consumes ≤1 mW power and 250 μA tunneling current per nm bending of cantilever beam structure. The inclusive length of the proposed device is 100 nm.

Analog and RF performance of doping-less tunnel FETs with $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$ Si 0.55 Ge 0.45 source

This paper reports studies of a doping-less tunnel field-effect transistor (TFET) with a $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$Si0.55Ge0.45 source structure aimed at improving the performance of charge-plasma-based doping-less TFETs. The proposed device achieves an improved ON-state current ($$I_{{\mathrm{ON}}} \sim {4.88} \times {10}^{-5}\,{\mathrm{A}}/\upmu {\mathrm{m}}$$ION~4.88×10-5A/μm), an $$I_\mathrm{ON}/I_\mathrm{OFF}$$ION/IOFF ratio of $${6.91} \times {10}^{12}$$6.91×1012, an average subthreshold slope ($$\hbox {AV-SS}$$AV-SS) of $$\sim $$~$${64.79}\,{\mathrm{mV/dec}}$$64.79mV/dec, and a point subthreshold slope (SS) of 14.95 mV/dec. This paper compares the analog and radio of frequency (RF) parameters of this device with those of a conventional doping-less TFET (DLTFET), including the transconductance ($$g_{{\mathrm{m}}}$$gm), transconductance-to-drain-current ratio $$(g_\mathrm{m}/I_\mathrm{D})$$(gm/ID), output conductance $$(g_\mathrm{d})$$(gd), intrinsic gain ($$A_{{\mathrm{V}}}$$AV), early voltage ($$V_{{\mathrm{EA}}}$$VEA), total gate capacitance ($$ C_{{\mathrm{gg}}}$$Cgg), and unity-gain frequency ($$f_{{\mathrm{T}}}$$fT). Based on the simulated results, the $$\hbox {Si}_{0.55}\hbox {Ge}_{0.45}$$Si0.55Ge0.45-source DLTFET is found to offer superior analog as well as RF performance.