Discrete Dopants Research Articles

Impact of the Figures of Merit (FoMs) Definitions on the Variability in Nanowire TFET: NEGF Simulation Study

In this article, we investigate the effect of variability in p-type nanowire tunnel FET (TFET) using quantum mechanical transport simulations. The simulations have been carried out using the Nano Electronics Simulation Software (NESS) from the University of Glasgow. Random discrete dopants (RDDs) and work-function variations (WFV) have been investigated in the simulations. Our statistical simulations reveal that key figures of merit (FoMs) such as the current variability generally decrease as the gate voltage decreases, the threshold voltage variability increases as the threshold current increases, and the dependences of these FoM variabilities on criteria become stronger with the switch characteristic ameliorated. Furthermore, it is interesting to find that the band offset in heterostructure can more or less alleviate the current variability, especially around the OFF-state.

Improved compact model extraction of statistical variability in 5 nm nanosheet transistors and applied to SRAM simulations

In this paper, we look at how artificial neural networks (ANNs) may be used to improve compact model extraction of statistical variability in 5 nm nanosheet transistors (NSTs) and how it can be applied to 6NST-static random access memory (SRAM) simulations. To begin, both the TCAD simulation platform and compact model of 3D n-type and p-type NST have been rigorously validated against the experimental data. The transfer characteristics curves of 1104 NST samples generated by metal gate granularity, random discrete dopants and line edge roughness are used to extract the important figures of merit (FoM) including ON-current (I ON), OFF-current (I OFF), threshold voltage (V TH) and subthreshold slope. Meanwhile, we can collect the main compact model parameters of these NST samples using our automatic extraction technique. Furthermore, a multi-layer ANN engine is trained to anticipate the important compact model parameters by entering FoMs, which significantly speeds up the automatic extraction. When we compare the prediction results to the genuine values, we discover that their correlation coefficients are all larger than 0.99. Finally, we simulated the 6NST-SRAM circuit and obtained its stability variation, with the help of extracted NST variability by the aforementioned speedup techniques.

Study of variability induced by random dopant fluctuation in Fe DS-SBTFET

This paper explores the affectability of random dopant fluctuation (RDF) on the performance of Ferroelectric Dopant Segregated Schottky Barrier (Fe DS-SB) TFET by utilizing 3-D TCAD simulation. The simulation technique involves the device bifurcation into rectangular coordinates where the doping charges are placed randomly as individual and discrete dopants. Threshold voltage varies significantly due to variation in source-channel dopant concentration. The dependency of threshold voltage standard deviation on various source doping concentration has been studied. Doping variability within the channel and drain regions mainly leads to alteration in ON state current. Moreover, the impact of temperature (300 K–500 K) on switching characteristics of the proposed device has been investigated.

Discrete, Shallow Doping of Semiconductors via Cylinder‐Forming Block Copolymer Self‐Assembly

AbstractBlock copolymer (BCP) self‐assembly‐assisted doping for semiconductors is used to achieve discrete doping with nanometer‐scale junction depth, high throughput, and large area coverage. As devices become smaller and more sophisticated, spatial control of dopants becomes more critical. A variety of doping methods, such as monolayer doping and δ‐doping, have been developed to replace the conventional doping method, ion‐implantation; however, lateral patterning of dopants relies on photo‐ or e‐beam lithography. To address these challenges, a self‐assembling dopant (boron)‐containing BCP is designed to directly pattern dopants on the nanometer scale. This method skips the lithography step and is compatible with directed self‐assembly approaches. The effect of the boron concentration in the BCP on the doping performance is systematically studied by changing the volume fraction of the boron‐containing block while keeping the domain spacing and the mesoscale morphology constant. Successful self‐assembly of the BCP into a hexagonally packed cylindrical morphology is confirmed by small‐angle X‐ray scattering and resonant soft X‐ray scattering with a 26 nm cylinder‐to‐cylinder distance. Doping silicon using these BCPs enables discrete doped areas with shallow (7–13 nm) junction depth as demonstrated by the depth profile of boron, and supported by a sheet resistance study.

Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element drift-diffusion/Monte Carlo simulator that includes 2D Schrödinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma ~{V}_{T}$ </tex-math></inline-formula> values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma {V}_{T}$ </tex-math></inline-formula> = 8 mV) and minimally influenced by the GER ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma {V}_{T} \approx 4$ </tex-math></inline-formula> mV). The variability of NS FETs makes them strong candidates to replace FinFETs.

Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes

Vertically stacked horizontal nanosheet gate-all-around transistors seem to be one of the viable solutions toward scaling down below sub-7nm technology nodes. In this work, we compare electrical performance, including variability studies of several horizontal nanosheet transistors toward transistor structure optimization. We explore the impacts of nanosheet width and thickness on the electrical performance and outline important design guidelines necessary for vertically stacked nanosheet FETs. An increase in the complexity of the stacked nanosheet structures can lead to significant device variability. Using numerical simulation, we study the characteristics fluctuations induced by the random discrete dopants (RDD) and metal grain granularity (MGG) in nanosheet gate-all-around (GAA) transistors. We use 3-D quantum-mechanically corrected transport models in the simulation. It is observed that the σVTH due to MGG variability is 12% higher than RDD variability while the RDD variability strongly influences the ION. The statistical simulation results predict that the presence of combined variability due to RDD and MGG strongly influences the threshold voltage variation (σVTH) in nanoscale devices. This approach may be applied to the different types of variability, the geometry of the device, including the vertical and lateral dimensions of the transistor, and biasing conditions.

Nanostructured active and photosensitive silica glass for fiber lasers with built-in Bragg gratings.

A nanostructured core silica fiber with active and photosensitive areas implemented within the fiber core is demonstrated. The photosensitivity, active and passive properties of the fiber can be independently shaped with this new approach. We show that discrete local doping with active ions in form of nanorods allow to obtain effective laser action as in case of continuous distribution of the ions in the core. Co-existing discrete photosensitive nanostructure of germanium doped silica determine single-mode performance and allow inscription of highly efficient Bragg grating over the entire core area. Each nanostructure do not degrade performance of other one since physical interaction between active and photosensitive areas are removed. As a proof of concept, we have designed and fabricated the nanostructured, ytterbium single-mode silica fiber laser with the Bragg grating inscribed in the entire core area. We demonstrated fiber laser with good quality of generated laser beam (M2=1.1) with lasing efficiency of 44% and inscribed Bragg grating with 98.5% efficiency and -18 dB contrast.

Quantum simulation investigation of work-function variation in nanowire tunnel FETs

The variability induced by the work-function variation (WFV) in p-type ultra-scaled nanowire tunnel FET (TFET) has been studied by using the Non-Equilibrium Green’s Function module implemented in University of Glasgow quantum transport simulator called NESS. To provide a thorough insight into the influence of WFV, we have simulated 250 atomistically different nanowire TFETs and the obtained results are compared to nanowire MOSFETs first. Our statistical simulations reveal that the threshold voltage (V th) variations of MOSFETs and TFETs are comparable, whereas the on-current (I on) and off-current (I off) variations of TFETs are smaller and higher, respectively in comparison to the MOSFET. Based on the results of the simulations, we have provided a physical insight into the variations of the I on and I off currents. Then, we compared the nanowire and Fin TFETs structures with different oxide thickness in terms of the WFV-induced variability. The results show that WFV has a strongest impact on the I off, and moderate effect on the I on and V th in nanowire TFET with smaller oxide thickness. Lastly, it is found that compared with the random discrete dopants, WFV is a relatively weaker variability source in ultra-scaled nanowire TFETs, especially from the point of view of I on variation.

A Worst-Case Analysis of Trap-Assisted Tunneling Leakage in DRAM Using a Machine Learning Approach

The variability in trap-assisted tunneling leakage that is enhanced by random discrete dopants (RDD) causes refresh failure in scaled 6F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> dynamic random-access memory (DRAM) cells. Thus, the worst-case leakage analysis is in high demand, but it requires significant computational cost. To overcome this issue, we performed 200 leakage variability simulations with RDD and a single trap to train a multi-layer neural-network (NN) model. Moreover, we propose a simulation flow using the NN model to find the worst RDD configuration among 5,000 candidates. We demonstrate the worst-case leakage can be found with 96.7% probability using only 5.5% computational cost compared to a full 3D TCAD statistical simulation approach.

Does the Threshold Voltage Extraction Method Affect Device Variability?

The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( $\mathrm {V_{TH}}$ ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in $\mathrm {V_{TH}}$ and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the $\mathrm {V_{TH}}$ distribution ( $\sigma \mathrm {V_{TH}}$ ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the $\mathrm {V_{TH}}$ extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.

An Analytical Breakdown Model for the SOI LDMOS With Arbitrary Drift Doping Profile by Using Effective Substrate Voltage Method

To elaborate on the relationship between sophisticated 2-D doping profile of drift region and device's breakdown behavior, a unified analytical model for the SOI LDMOS is developed in this paper. The Effective Substrate Voltage (ESV) concept is proposed so that the derivation of electric field and breakdown voltage can be simplified significantly. The ESV indicates that the influence of 2-D doping in the drift region can be equivalent to a virtual substrate potential. By using the proposed model, the role of 2-D drift doping, both continuous or discrete doping profile, in SOI LDMOSs' off-state breakdown behavior is investigated along with the TCAD simulations and experimental results. The good agreement between the analytical, measured and simulated results validates the accuracy of the developed model. A unified RESURF criterion is derived to idealize the electric field in the drift region and therefore maximize the breakdown voltage by optimizing the lateral and vertical drift doping profiles and geometric parameters. The proposed approach provides a universally applicable tool to explore the breakdown mechanism of SOI LDMOS with various drift doping profiles.

Machine Learning Approach for Predicting the Effect of Statistical Variability in Si Junctionless Nanowire Transistors

This letter investigates the possibility to replace numerical TCAD device simulations with a multi-layer neural network (NN). We explore if it is possible to train the NN with the required accuracy in order to predict device characteristics of thousands of transistors without executing TCAD simulations. Here, in order to answer this question, we present a hierarchical multi-scale simulation study of a silicon junctionless nanowire field-effect transistor (JL-NWT) with a gate length of 150 nm and diameter of an Si channel of 8 nm. All device simulations are based on the drift-diffusion (DD) formalism with activated density gradient (DG) quantum corrections. For the purpose of this letter, we perform statistical numerical experiments of a set of 1380 automictically different JL-NWTs. Each device has a unique random distribution of discrete dopants (RDD) within the silicon body. From those statistical simulations, we extract important figures of merit (FoM) such as OFF-current (IOFF) and ON-current (ION), subthreshold slope (SS), and voltage threshold (VTH). Based on those statistical simulations, we train a multi-layer NN and we compare the obtained results with a general linear model (GLM). This shows the potential of using NN in the field of device modeling and simulation with a potential application to significantly reduce the computational cost.

Fin Shape Dependence of Electrostatics and Variability in FinFETs

The performance of advanced nanoscale devices is limited by different process variability issues, including patterning proximity effects. Most manufactured fin-shaped field-effect transistors (FinFETs) have some imperfections in the fin shape due to imperfections in lithography and deformation due to other high-temperature process steps. In this work, full three-dimensional (3D) device simulations are performed to study the effects of such variability in the fin shape on the electrostatics of trigate FinFETs. Variability due to random discrete dopants (RDDs) and metal grain granularity (MGG) is considered separately and in combination. The device threshold voltage variation due to RDDs and MGG is critically examined. Finally, we calculate the mean and standard deviation of these parameters (QQ plots) to quantify the variability. It is shown that there is a strong correlation between the drain-induced barrier lowering (DIBL) and random discrete dopant position in the channel.

Stress-Induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7 nm Technology Nodes

The epitaxially grown SiGe source/drain stressor (e-SiGe) technique has emerged to be a consistent performance booster for advanced devices below the 14 nm technology node. At nanoscale, the omnipresent residual stress is now becoming an important source of variability in advanced VLSI technologies that influence the circuit performance. Also, in deeply-scaled technologies, process and environment variations become other sources of variabilities. In this paper, we study the stress-induced variability in aggressively scaled (at 7 N) Si-channel FinFETs with epitaxially grown SiGe stressors in the source and drain regions. The stress distribution analysis is performed with the help of Technology CAD mechanical stress simulations. At first, we calibrate our simulation results with available experimental data. We generate the stress maps in FinFETs with various scaled dimensions of fin length, height and width. The effects of residual strain/stress on variability due to metal gate granularity (MGG) and random discrete dopant (RDD) in strain-engineered FinFETs (with 50 configurations) have been investigated. Furthermore, the device threshold voltage variation due to RDD and MGG are critically examined. Finally, we calculate the mean and standard deviation of these parameters (QQ plots) to quantify the variability.

DFT/NEGF study of discrete dopants in Si/III–V 3D FET

In this work, electron densities around dopants in Si and GaAs have been calculated using density functional theory (DFT) calculations. These extracted densities have been used to describe dopants in an in-house non-equilibrium Green functions device simulator. The transfer characteristics of nanowire gate all around field effect transistor have been calculated using DFT electron densities. These transport calculations were compared with those using a point charge model of the dopant. The dopants are located in the middle of the channel of the device. Specifically, DFT calculations of a 512 atom Si supercell with a single impurity atom have been carried out, both phosphorous and boron atoms have been used as donor and acceptor impurities respectively. The calculations were repeated on a gallium arsenide supercell, where the silicon atom substituted gallium and arsenide to act as donor and acceptor respectively. We found that for donors and acceptors, the DFT charge distribution extends similarly in both materials. In addition, the relaxed structure produces a 50% larger spread of electronic charge as compared with unrelaxed Si and GaAs. The extracted current voltage characteristics of the devices are altered significantly using the charge density obtained by DFT. At 0.7 V the current in Si is 20% larger using the DFT charge density compared to the point charge model for donors. Whereas the current using the point charge model in GaAs is 2.5 times larger than the distributed charge. Devices exhibit substantial tunnelling currents for donors and acceptors irrespective of the model of the dopant considered. In GaAs, this was 76% using a point charge and 78% using the distributed charge when using a donor; 61% and 68% in Si respectively. The tunnelling current using acceptors for Si was 100% and 99% using GaAs for both models.

Variability Predictions for the Next Technology Generations of n-type SixGe1-x Nanowire MOSFETs.

Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs.

Random Dopant-Induced Variability in Si-InAs Nanowire Tunnel FETs: A Quantum Transport Simulation Study

In this letter, we report a quantum transport simulation study of the impact of random discrete dopants (RDDs) on Si-InAs nanowire p-type Tunnel FETs. The band-to-band tunneling is simulated using the non-equilibrium Green’s function formalism in effective mass approximation, implementing a two-band model of the imaginary dispersion. We have found that RDDs induce strong variability not only in the OFF-state but also in the ON-state current of the TFETs. Contrary to the nearly normal distribution of the RDD-induced ON-current variations in conventional CMOS transistors, the TFET’s ON-currents variations are described by a logarithmic distribution. The distributions of other figures of merit (FoM) such as threshold voltage and subthreshold swing are also reported. The variability in the FoM is analyzed by studying the correlation between the number and the position of the dopants.

Analog Figure-of-Merits Comparison of Gate Workfunction Variability and Random Discrete Dopant Between Inversion-Mode and Junctionless Nanowire FETs.

The analog figure-of-merits (FOMs) of conventional inversion-mode (IM) and junctionless (JL) NanoWire Field Effect Transistor (NWFET) have been investigated, considering the gate Work-Function Variability (WFV) and Random Discrete Dopant (RDD) using 3-dimensional (3D) TCAD simulation. While the JL-NWFET shows higher immune to WFV on analog FOMs, it can be easily affected by RDD due to higher channel doping level. On the other hand, the IM-NWFET shows stronger correlation between transconductance (gm) and gate capacitance (Cgg), leading to similar variation in cut-off frequency (ft) even though it shows larger gm and Cgg variation compared to JL-NWFET.

Electric-field tuning of the valley splitting in silicon corner dots

We perform an excited state spectroscopy analysis of a silicon corner dot in a nanowire field-effect transistor to assess the electric field tunability of the valley splitting. First, we demonstrate a back-gate-controlled transition between a single quantum dot and a double quantum dot in parallel which allows tuning the device into corner dot formation. We find a linear dependence of the valley splitting on back-gate voltage, from 880 μeV to 610 μeV with a slope of −45 ± 3 μeV/V (or equivalently a slope of −48 ± 3 μeV/(MV/m) with respect to the effective field). The experimental results are backed up by tight-binding simulations that include the effect of surface roughness, remote charges in the gate stack, and discrete dopants in the channel. Our results demonstrate a way to electrically tune the valley splitting in silicon-on-insulator-based quantum dots, a requirement to achieve all-electrical manipulation of silicon spin qubits.

DC/AC/RF Characteristic Fluctuations Induced by Various Random Discrete Dopants of Gate-All-Around Silicon Nanowire n-MOSFETs

In this paper, we explored the characteristic fluctuations induced by various random discrete dopants (RDDs) on gate-all-around silicon nanowire metal–oxide semiconductor field-effect transistors. A 3-D quantum-mechanically corrected transport model was employed to analyze the simulated devices. The statistical results indicate that the variation of threshold voltage ( ${V}_{\text {th}}$ ) not only can be reduced from 28.6% to 10.7% without channel doping and penetration from the source/drain into the channel, but also the variation of 3-dB frequency can be reduced from 8% to 2.7% due to the reduction of the variation of ${V}_{\text {th}}$ . We reported that the high-frequency characteristic fluctuations (voltage gain and cutoff frequency) were dominated by electron mobility. This caused by RDDs from the drain extension exhibited less variability than that caused by RDDs from the source extension due to a reduced injection velocity near the S side and a negligible difference in the electron saturation velocity near the D side. This paper provides pertinent information on the design of high-frequency amplifier circuits in relation to devices with RDDs induced by variations in the semiconductor process.