Discrete Dopants Research Articles

Comparison of Random Dopant and Gate-Metal Workfunction Variability Between Junctionless and Conventional FinFETs

This letter reports, for the first time, the performance of a junctionless (JL) FinFET in the presence of random grain orientation-induced metal workfunction variability (WFV), as compared with a similarly sized conventional FinFET. Relative impact of random discrete dopant (RDD)-induced variability and WFV are also compared between such devices by the use of a 3-D numerical device simulator. Numerical values of standard deviation of different device parameters reveal that the performance parameters of a JL FinFET are significantly affected by WFV. In addition, the impact of the RDD, as compared with WFV, is larger in JL devices, as expected.

Effect of Random, Discrete Source Dopant Distributions on Nanowire Tunnel FETs

The finite number, random placement, and discrete nature of the dopants in the source of an InAs nanowire tunnel field-effect transistor affect the drive current and the inverse subthreshold slope. The impact of source scattering is negligible, since the current is limited by the interband tunneling. The most significant effect of the discrete dopants is to create variations of the electric fields in the tunnel barrier, which cause variations in the current. The relative variation in the ON current decreases as the average doping density and/or nanowire diameter increases. Results from full self-consistent nonequilibrium Green's function calculations and semiclassical calculations are compared.

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20-nm technology node. In this paper, their impacts on device figures of merit are studied through comprehensive 3-D simulation. It is found that raised drain-bias can exacerbate threshold-voltage fluctuations, mainly due to LER and RDD. Subthreshold slope (SS) variations resulting from each variation source is studied: RDD and LER generate most of the SS variation and are primarily responsible for its skew. Drain induced barrier lowering (DIBL) is examined against each intrinsic variation source, and RDD and LER are found to cause most of the DIBL variability. The correlation of DIBL with threshold-voltage is fully analysed with respect to each source of statistical variability and reliability. Except for LER, all major sources of variability exhibit de-correlation of DIBL against threshold-voltage.

An analytical approach for the determination of the lateral trap position in ultra-scaled MOSFETs

We propose a new method to determine the lateral trap position in ultra-scaled MOSFETs with a precision of less than 1 nm. The method is based on an analytical model which links the surface potential in the presence of a discrete trap to the drain voltage. We demonstrate that the dependence between the surface potential in the damaged region of the channel and the drain voltage is quasi-linear. The unique slope of this dependence corresponds to a particular lateral trap position and can thus be used as a fingerprint to locate the trap. A high accuracy is reached due to a negligibly small impact of the random dopant fluctuations on the slope magnitude. To verify our analytical approach we employ standard technology computer aided design (TCAD) methods, including random discrete dopants for both n- and p-MOSFETs with various channel lengths.

Metal Oxide Resistive Switching: Evolution of the Density of States Across the Metal-Insulator Transition

We report the study of gold-SrTiO3 (STO)-gold memristors where the doping concentration in STO can be fine-tuned through electric field migration of oxygen vacancies. In this tunnel junction device, the evolution of the density of states (DOS) can be followed continuously across the metal-insulator transition (MIT). At very low dopant concentration, the junction displays characteristic signatures of discrete dopant levels. As the dopant concentration increases, the semiconductor band gap fills in but a soft Coulomb gap remains. At even higher doping, a transition to a metallic state occurs where the DOS at the Fermi level becomes finite and Altshuler-Aronov corrections to the DOS are observed. At the critical point of the MIT, the DOS scales linearly with energy N(ϵ)∼ϵ, the possible signature of multifractality.

Impact of random discrete dopant in extension induced fluctuation in gate–source/drain underlap FinFET

In this work, three dimensional technology computer-aided design (TCAD) simulations are performed to investigate the impact of random discrete dopant (RDD) including extension induced fluctuation in 14 nm silicon-on-insulator (SOI) gate–source/drain (G–S/D) underlap fin field effect transistor (FinFET). To fully understand the RDD impact in extension, RDD effect is evaluated in channel and extension separately and together. The statistical variability of FinFET performance parameters including threshold voltage (Vth), subthreshold slope (SS), drain induced barrier lowering (DIBL), drive current (Ion), and leakage current (Ioff) are analyzed. The results indicate that RDD in extension can lead to substantial variability, especially for SS, DIBL, and Ion and should be taken into account together with that in channel to get an accurate estimation on RDF. Meanwhile, higher doping concentration of extension region is suggested from the perspective of overall variability control.

Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET

A 3-D quantum-corrected drift-diffusion (DD) simulation study of three sources of statistical variability, including discrete random dopants (RDs), line-edge roughness (LER), and metal gate workfunction (MGW) was performed for a 14-nm gate length In0.53Ga0.47As FinFET in the subthreshold region using Fermi-Dirac statistics. This paper has been done at both low (0.05 V) and high drain biases (0.6 V). The LER variability is characterized by the root mean square amplitude (Δ) and correlation length (Λ), and the MGW variability by the metal grain size (GS). The RD-induced variation σ VT = 6 mV is similar to that observed in Si SoI FinFETs. The LER-induced threshold voltage variations (σ VT <; 6 mV) are similar to the RD variations when Δ = 1 nm, and smaller than the observed in Si SoI FinFETs (18 mV). For larger A, the LER exhibits σ VT ranging from 11 mV when Λ = 10 nm and Δ = 2 nm to 19 mV when Λ = 20 nm and Δ = 3 nm. The MGW variations are the dominant source of variability in the subthreshold characteristics, the σ VT ranges from 106 mV when GS = 10 nm to 43 mV when GS = 3 nm, which is larger than those observed in equivalent TiN metal-gate Si FinFETs.

Investigation of discrete dopant induced variability in silicon nanowire MOSFETs using 3D simulation

Impact of discrete doping in n-type gate-all-around silicon nanowire transistors is studied using 3D numerical simulation with quantum mechanical effect accounted for. We investigate the devices in the sub-22 nm technology node based on an assumption of sphere dopants with 1 nm diameter. Comprehensive study of equal random dopant probability in the channel is first reported. Our results show that the silicon nanowire FETs have more severe threshold variation when the random dopant is located in the centre of the channel than is located near source/drain boundary. The predicted threshold voltage variability ranges from 0.19 V to 0.26 V while most cases have threshold voltages below 0.23 V. The leakage current variability is within an order of magnitude and the output current variability is within one hundred micro amperes.

Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology

This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence of statistical variability and reliability impact. As statistical variability sources random discrete dopants, gate-edge roughness, fi-edge roughness, metal-gate granularity and random interface trapped charges in N/PBTI are considered.

Comparative Simulation Analysis of Process-Induced Variability in Nanoscale SOI and Bulk Trigate FinFETs

This paper presents a comprehensive simulation study of the process and statistical variability in 16-nm technology node bulk and silicon-on-insulator (SOI) fin field effect transistors (FinFETs). The devices are carefully designed to offer good manufacturability while meeting the performance requirements of the 16-nm technology. First, the sensitivity of the two types of FinFETs to process- induced channel length, fin-width, and fin-height variability is carefully investigated and compared based on the threshold voltage, OFF-current, and overdrive current sensitivity. Possible improvement of the SOI substrate design for reduction of the SOI FinFET sensitivity to fin-width variation is also discussed. The individual and combined impact of the relevant statistical variability sources including random discrete dopants (RDDs), fin-line edge roughness, gate-line edge roughness, and metal gate granularity are studied and compared for the nominal 25-nm gate length FinFET designs.

Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs

This paper presents a comprehensive simulation study of the interactions between long-range process and short-range statistical variability in a 14-nm technology node silicon-on-insulator FinFET. First, the individual and combined impact of the relevant variability sources, including random discrete dopants, fin line edge roughness (LER), gate LER, and metal gate granularity are studied for the nominal 20-nm physical gate-length FinFET design. This is followed by a comprehensive study of the interactions of the channel length, fin width and fin height systematic process variations with the combined statistical variability sources. The simulations follow a 3×3×3=27 experiment design that covers the process variability space, and 1000 statistical simulations are carried out at each node of the experiment. Both metal-gate-first and metal-gate-last technologies are considered. It is found that statistical variability is significantly dependent on the process-induced variability. The applicability of the Pelgrom law to the FinFET statistical variability, subject to long-range process variations, is also examined. Mismatch factor is strongly dependent on the process variations.

Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory

A comprehensive numerical study of threshold voltage fluctuation (ΔVT) in scaled NAND flash memory caused by random telegraph noise (RTN) and discrete dopant fluctuation (RDF) in both the channel and the cell-to-cell space [source/drain (S/D)] region was carried out. Following a three-dimensional (3D) Monte Carlo (MC) procedure, the statistical distribution of ΔVT is estimated, considering the effects of both the random placement of discrete doping atoms and a discrete single trap at the tunnel oxide/substrate interface. The result demonstrates the significant influence of the doping in the S/D regions. For the cells with and without an S/D junction, the electron concentration in the S/D region is determined by the pass voltage of the unselected cell (Vpass) and the neighboring cell VT (VT(n)), owing to the fringing fields of neighboring floating gates (FGs). As a result, ΔVT increases in the S/D region as Vpass - VT(n) decreases. The fluctuation amplitude strongly depends on the [single-trap RTN] position along the cell length (L) and width (W) directions. For the cell shape with rounding of the active area (AA) at the shallow trench isolation (STI) edge, the results indicate that the high ΔVT area moves from the AA edge towards the center area along the W-direction.

Analytical models of lateral power devices with arbitrary vertical doping profiles in the drift region

By solving the 2D Poisson's equation, analytical models are proposed to calculate the surface potential and electric field distributions of lateral power devices with arbitrary vertical doping profiles. The vertical and the lateral breakdown voltages are formulized to quantify the breakdown characteristic in completely-depleted and partially-depleted cases. A new reduced surface field (RESURF) criterion which can be used in various drift doping profiles is further derived for obtaining the optimal trade-off between the breakdown voltage and the on-resistance. Based on these models and the numerical simulation, the electric field modulation mechanism and the breakdown characteristics of lateral power devices are investigated in detail for the uniform, linear, Gaussian, and some discrete doping profiles along the vertical direction in the drift region. Then, the mentioned vertical doping profiles of these devices with the same geometric parameters are optimized, and the results show that the optimal breakdown voltages and the effective drift doping concentrations of these devices are identical, which are equal to those of the uniform-doped device, respectively. The analytical results of these proposed models are in good agreement with the numerical results and the previous experimental results, confirming the validity of the models presented here.

The intrinsic parameter fluctuation on high-κ/metal gate bulk FinFET devices

In this work, based on the experimentally calibrated 3D device simulation, we for the first time estimate the impact of intrinsic parameter fluctuation on the electrical characteristic of 16-nm-gate TiN/HfO2 bulk FinFETs. The sources of intrinsic parameter fluctuation include the random discrete dopants, interface traps and work function differences, simultaneously. The full 3D simulated threshold voltage fluctuation, induced by the aforementioned random sources simultaneously, is 26.2 mV for the N-type bulk FinFET (and is 55.5 mV for the planar N-MOSFET). For the N-type bulk FinFET, the statistical sum of these fluctuations is 9.5% (and is 12.3% for the planar device) overestimation, compared with the full 3D simulation. One of the main reasons is the independence assumption on these random variables is destroyed owing to interactions to different extents among RDs, ITs and WKs. The coupled surface potentials cannot be simply estimated by using their statistical sum of individual random source. Under the same threshold voltage, compared with the result of the planar MOSFETs, more than 50% reduction on the threshold voltage fluctuation of the explored bulk FinFETs is observed owing to the benefit of 3D structural nature.

Comprehensive study of the statistical variability in a 22 nm fully depleted ultra-thin-body SOI MOSFET

A comprehensive study of statistical variability (SV) in scaled, fully-depleted (FD) SOI n-channel MOSFET with a physical gate length of 22nm is reported. The impact of random discrete dopant (RDF), line edge roughness (LER) and metal gate granularity (MGG) on threshold voltage (VTH), drain-induced-barrier-lowering (DIBL) and on-current (Ion) are analyzed both individually and combined together. Results indicate that although MGG is the dominated variability source in the FD-SOI transistor, RDF has critical impact on the on-current variability. Moreover, the combination of RDF and LER can still dramatically modulate short channel effect behavior in the transistor.

Impact of Junction Nonabruptness on Random-Discrete-Dopant Induced Variability in Intrinsic Channel Trigate Metal–Oxide–Semiconductor Field-Effect Transistors

Using full three-dimensional (3D) technology computer-aided design (TCAD) simulations, we present a comprehensive statistical study on the random discrete dopant (RDD) induced variability in state-of-the-art intrinsic channel trigate MOSFETs. This paper is focused on the RDD variability sources that are introduced by dopant diffusion from highly doped source/drain (S/D) regions into the undoped channel region, which is referred to as junction nonabruptness (JNA). By considering a realistic lateral doping profile in the channel and evaluating the impact of JNA on the variability of performance parameters such as threshold voltage (Vth), subthreshold slope (SS), drain-induced barrier lowering (DIBL), on current (Ion), and off current (Ioff), we show that the effect of JNA can lead to substantial device variations. The nonnegligible influence of JNA puts limitations on device scaling, which is also investigated in this paper.

Simulation of a single dopant nanowire transistor

ABSTRACTNowadays the silicon technology is capable of delivering sub-10 nm devices where ‘every atom counts’. Manipulation of atoms with high precision on such a scale, in principle, can lead to technological innovations, such as transistors with extremely short gate length, quantum computing components and optoelectronic devices. One possible strategy to create this next generation of devices is to precisely place individual discrete dopants (such as phosphorous atoms) in a nanoscale transistor.In this paper, we report a systematic study of quantum transport simulation of an impact that precisely positioned dopants have on the performance of ultimately scaled gate-all-around silicon nanowire transistors (SNWT) designed for digital circuit applications. Due to strong inhomogeneity of self-consistent electrostatic potential, a full 3-D real-space Non Equilibrium Green’s Function (NEGF) formalism is used. The simulations are carried out for an n-channel NWT with a 2.2 x 2.2 nm2 cross-section and a 6 nm channel length, where locations of precisely arranged dopants in the source drain extensions and in the channel region have been varied. The individual dopants act as localized scatters and, hence, impact of electron transport is directly correlated to the position of the single dopants. As a result, a large variation in the ON-current and modest variation of the subthreshold slope are observed in the ID-VG characteristics when comparing devices with microscopically different discrete dopant configuration. Introducing of channel surface roughness in the Ch Sym 1 wire induces a threshold voltage shift and ON-current variation in the device due to scattering. The variations of the current-voltage characteristics are analyzed with reference to the behaviour of the transmission coefficients. Our calculations provide guidance for a future development of the next generation components with sub-10 nm dimensions for the semiconductor industry.

Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits

This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$S.S.$</tex></formula> ) and comparable trap-induced <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{T}$</tex></formula> shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm dd})$</tex></formula> , the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way nand, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sim$</tex></formula> 24%–27% and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\sim$</tex></formula> 13%–15% variations in leakage and delay at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{ \rm dd} = \hbox{0.4}\ \hbox{V}$</tex></formula> , respectively, for the logic circuits evaluated.

Statistical device simulation of physical and electrical characteristic fluctuations in 16-nm-gate high-κ/metal gate MOSFETs in the presence of random discrete dopants and random interface traps

We estimate the effects of random discrete dopants (RDs) and random interface traps (ITs) on physical and electrical characteristic fluctuations of 16-nm-gate high-κ/metal gate (HKMG) metal–oxide-semiconductor field effect transistors (MOSFETs). Two-dimensional (2D) random ITs at the hafnium oxide (HfO2)/silicon interface and 3D RDs inside the silicon channel of the 16-nm-gate HKMG MOSFETs are simultaneously incorporated into an experimentally validated 3D device simulation to quantify the RDs-and-ITs-fluctuated characteristics. The random effect of the combined RDs and ITs induces rather different fluctuation in the threshold voltage, the on-/off-state current, and the gate capacitance in the 16-nm-gate HKMG MOSFETs. The surface potential, DC and AC characteristic fluctuations are affected to different extents by the random combinatorial RDs and ITs. Nonlinearly correlated RDs and ITs violate the statistical assumption of independent identical distributions between the RDs- and ITs-induced random variables. Consequently, for the studied 16-nm-gate HKMG N-MOSFETs, the threshold voltage fluctuation induced by the combined RDs and ITs is 11% less than their statistical sum due to local interaction of surface potentials resulting from the RDs and ITs simultaneously. Similarly, it is about 8.9% for the P-MOSFET devices. Depending upon random position and number of the combined RDs and ITs, overestimation or underestimation between the statistical sum of variances and the 3D device simulation is also observed for the drain current and the gate capacitance.

Simulation Study of Dominant Statistical Variability Sources in 32-nm High- $\kappa$/Metal Gate CMOS

Comprehensive 3-D simulations have been carried out and compared with experimental data highlighting the dominant sources of statistical variability in 32-nm high-κ/metal gate MOSFET technology. The statistical variability sources include random discrete dopants, line edge roughness, and metal gate granularity. Their relative importance is highlighted in the numerical simulations. Excellent agreement is achieved between the simulated and measured standard deviation of the threshold voltage.