Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs

Abstract

This paper presents a comprehensive simulation study of the interactions between long-range process and short-range statistical variability in a 14-nm technology node silicon-on-insulator FinFET. First, the individual and combined impact of the relevant variability sources, including random discrete dopants, fin line edge roughness (LER), gate LER, and metal gate granularity are studied for the nominal 20-nm physical gate-length FinFET design. This is followed by a comprehensive study of the interactions of the channel length, fin width and fin height systematic process variations with the combined statistical variability sources. The simulations follow a 3×3×3=27 experiment design that covers the process variability space, and 1000 statistical simulations are carried out at each node of the experiment. Both metal-gate-first and metal-gate-last technologies are considered. It is found that statistical variability is significantly dependent on the process-induced variability. The applicability of the Pelgrom law to the FinFET statistical variability, subject to long-range process variations, is also examined. Mismatch factor is strongly dependent on the process variations.