Digital Signal Processing Systems Research Articles

Complex of algorithms for fast determination of the parameters of motion of high-speed vessels in the digital signal processing system of a space synthetic aperture radar

The article presents the main considerations for determining the tangential velocity of high-speed vessels in the digital signal processing system of a space synthetic aperture radar with an amplitude-phase program discriminator in the azimuth channel. The article suggests a complex of algorithms for fast determination of the parameters of motion of high-speed vessels in the digital signal processing system of a space synthetic aperture radar. The article contains the results of semi-natural experiments that confirm the reliability of the algorithms and their effectiveness in solving the problem of observing the sea surface.

Fault Classification and Diagnosis Approach Using FFT-CNN for FPGA-Based CORDIC Processor

Within the realm of digital signal processing and communication systems, FPGA-based CORDIC (Coordinate Rotation Digital Computer) processors play pivotal roles, applied in trigonometric calculations and vector operations. However, soft errors have become one of the major threats in high-reliability FPGA-based applications, potentially degrading performance and causing system failures. This paper proposes a fault classification and diagnosis method for FPGA-based CORDIC processors, leveraging Fast Fourier Transform (FFT) and Convolutional Neural Networks (CNNs). The approach involves constructing fault classification datasets, optimizing features extraction through FFT to shorten the time of diagnosis and improve the diagnostic accuracy, and employing CNNs for training and testing of faults diagnosis. Different CNN architectures are tested to explore and construct the optimal fault classifier. Experimental results encompassing simulation and implementation demonstrate the improved accuracy and efficiency in fault classification and diagnosis. The proposed method provides fault prediction with an accuracy of more than 98.6% and holds the potential to enhance the reliability and performance of FPGA-based CORDIC circuit systems, surpassing traditional fault diagnosis methods such as Sum of Square (SoS).

4:2 Compressor Design for Low Leakage Applications in FinFET Technology

The increased short-channel effects in the ultra-nanoscale regime limit the operation of complementary metal oxide semiconductor (CMOS) technology. To combat the issues in the ultra-nanoscale regime, fin-shaped field effect transistor (FinFET) technology is the best choice because of its numerous advantages over CMOS technology. FinFET enhances the further scaling of the devices and control over the channel. Therefore, this research paper presents the implementation of a low leakage 4:2 compressor in FinFET technology. A compressor is a general block, especially used in multiplier units and hence in digital signal processing (DSP) systems. The design of the low power compressor improves the overall efficiency of the DSP systems. An extensive study of the proposed low power 4:2 compressor at 7 nm technology node is done in the paper. Mentor Graphics tools are used for the circuit simulations and analyzes. The key parameters, such as leakage power, delay, power delay product (PDP), and the process voltage temperature (PVT) variations, are estimated for the performance evaluation. The proposed 4:2 compressor saves 87.33% of leakage power and is 75.90% more energy efficient compared to its conventional counterpart.

Review on Advances in VLSI Multipliers

This abstract explores recent advancements in multiplier design, addressing the critical factors of speed, power consumption, and layout regularity. The emphasis is on achieving optimal trade-offs to meet the increasing demands of high-performance digital systems. As digital signal processing (DSP) systems continue to evolve, the reliance on hardware multiplication becomes paramount for achieving high data throughput. The presented advancements in multiplier design contribute to the development of compact, high-speed, and low-power Very Large-Scale Integration (VLSI) implementations, catering to the diverse needs of modern digital systems.

Analytical method of DC input impedance for stability analysis of IPM motor drive system

AbstractThis paper proposes an analytical calculation method of frequency characteristics of DC input impedances of an IPM motor drive system for design and stability analysis by the impedance method. The proposed method is based on an averaged frequency model linearized at an operating point. The developed small‐signal model considers control principles and mechanical perturbations. It is an analog and digital mixed model which is controlled by a digital signal processor system. Analysis examples of frequency characteristics for the impedance method by the proposed method are investigated and validated analytically and experimentally.

VLSI Implementation of 3-Parallel FIR Filters through Coefficient Symmetry Property and Fast FIR Algorithm

In multirate digital signal processing systems, polyphase filters are frequently used. The challenges in multirate digital signal processing systems primarily relate to efficiently processing signals at different rates while maintaining high-quality output. These challenges include computational complexity, power consumption, and signal delay. The coefficient symmetry property plays a key role in systematically arranging of filter taps in symmetric manner to improve operating efficiency. With a major focus on using the coefficient symmetry characteristic, this paper addresses the VLSI implementation of traditional Type-1 polyphase FIR filters. Furthermore, this paper incorporated 3-parallel FIR filters especially for sequences with odd lengths in order to take full advantage of the coefficient symmetry characteristic. The Fast FIR Algorithm (FFA) method is used to increase overall efficiency. Furthermore, in order to achieve better performance, a modified FFA technique is introduced to enhance overall performance. The paper thoroughly investigates important VLSI factors, such as power consumption, utilization, and delay, and shows how, by utilizing coefficient symmetry and applying this modified FFA technique, filters that are optimized for both power consumption and area utilization are able to be implemented. The results illustrate a significant reduction in both area and power consumption, particularly for longer filters, attributed to the reduced number of multiplication operations inherent in the fast FIR algorithm approach. Additionally, image processing application using 3x3 FIR filter is executed.

Development of a high-speed digital pulse signal acquisition and processing system based on MTCA for liquid scintillator neutron detector on EAST

Development of a high-speed digital pulse signal acquisition and processing system based on MTCA for liquid scintillator neutron detector on EAST

Analysis of System Capacity and Spectral Efficiency of Fixed-Grid Network

In this article, the performance of a fixed grid network is examined for various modulation formats to estimate the system's capacity and spectral efficiency. The optical In-phase Quadrature Modulator (IQM) structure is used to build a fixed grid network modulation, and the homodyne detection approach is used for the receiver. Data multiplexing is accomplished using the Polarization Division Multiplexed (PDM) technology. 100 Gbps, 150 Gbps, and 200 Gbps data rates are transmitted under these circumstances utilizing various modulation formats. Various pre-processing and signal recovery steps are explained by using modern digital signal processing systems. The achieved spectrum efficiencies for PM-QPSK, PM-8 QAM, and PM-16 QAM, respectively, were 2, 3, and 4 (bits/s)/Hz. Different modulation like PM-QPSK, PM-8-QAM, and PM-16-QAM each has system capacities of 8-9, 12-13.5, and 16-18 Tbps and it reaches transmission distances of 3000, 1300, and 700 kilometers with acceptable Bit Error Rate (BER≤ 2× 10-3 ) respectively. Peak optical power for received signal detection and full width at half maximum is noted for the different modulations under a fixed grind network.

A Nonlinear Function Logic Computing Architecture With Low Switching Activity

Nonlinear functions are widely involved in modern digital signal processing systems, which are usually calculated by polynomial approximation, CORDIC algorithm, or look-up tables. Due to the quite complex logic computing architectures, these methods suffer from high switching activity of logic elements, resulting in tremendous dynamic power consumption. Reducing the switching activity is believed an efficient way to save dynamic power. In this brief, we first analyzed and proved the low switching activity feature of the conventional unary number representation. Afterward, a novel multi-hot unary number representation method and the corresponding logic computing architecture with low switching activity are proposed for nonlinear function, which significantly reduces switching activity and power consumption. Moreover, the proposed nonlinear function logic computing architecture is extended to single input multiple output nonlinear function calculation, which shares the multi-hot encoder to further reduce the hardware cost. According to the post-synthesis power evaluation using PrimePower tools, the proposed architecture achieves significant switching activity and dynamic power reduction compared to conventional computing architectures.

Quantization error for weak RF simultaneous signal estimation

In a congested signal environment, it is difficult to obtain estimates of weak RF signal parameters. Determining signal parameter estimates in real time is a challenge for electronic warfare receivers that aim to receive multiple simultaneous signals. Prior work provided estimates of weak signal parameters (weak signal frequency and weak signal amplitude) without taking into account any error introduced by analog-to-digital converters that are inherently part of digital signal processing systems. In order to obtain realistic estimates, we need to take error introduced by an ADC into account. The primary aim of this paper is to quantify error introduced by a single ideal ADC as a function of angle. This paper presents a method to estimate angle resolution and quantization levels in N-bit analog-to-digital converters (ADCs) for use in a weak radiofrequency (RF) simultaneous signal estimation process. The paper quantifies the error in the angle quantization of an N-bit ADC for an input complex signal that is the instantaneous frequency obtained for the situation in which there are two simultaneous signals (with one strong signal and one weak signal) in a weak RF simultaneous signal estimation process. The presented method describes the process to determine the angle quantization range, angle quantization uncertainty, and angle quantization error. This approach has potential applications in electronic warfare (EW) systems. The approach also has potential for assessing ADC performance for measurements that approach the quantum limit. Results are presented for 1-bit, 2-bit, 3-bit, and 10-bit ADCs.

Design of a Digital Array Signal Processing System with Full Array Element

For the application of a digital array signal processing system with a high sampling rate and large bandwidth, and considering the constraints of limited resources (performance, volume, power consumption, weight, etc.), this paper proposes a design and implementation method of broadband digital array signal processing system based on radio frequency system on a chip. The system focuses on multi-channel synchronization under a high sampling rate and multi-channel amplitude and phase calibration under large bandwidth to form an all-digital, low-power, multi-channel, high-speed, large bandwidth hardware platform suitable for broadband digital array signal processing. Through the implementation of the Multiple-Input Multiple-Output phased-array digital beamforming algorithm, the test conducted verifies that the system has superior signal processing performance of the broadband digital array.

Implementation of a Butterworth digital filter using Python libraries

Formulation of the problem. In digital signal processing, noise refers to unwanted or random elements of a signal that can distort or corrupt its information content. Such noise can arise from various sources, including electromagnetic interference, thermal noise, quantization errors, and degradation of the transmission channel. It is necessary to deal with noise in a digital signal, as it can degrade the quality and reliability of the signal, lead to errors, distortions and loss of information. Moreover, noise can limit the performance of many digital signal processing systems, such as communications and audio processing systems. Therefore, various methods and algorithms have been developed to reduce noise and improve the quality of digital signals, the main of which is filtering. Target. Increasing the efficiency of digital signal processing systems using filters that allow you to programmatically change the signal filtering parameters. Development of a signal processing system in the Python programming language that implements the Butterworth digital filter algorithm. Results. The architectures of filters with infinite impulse response (IIR filters), features of the Butterworth filter are considered. A software model of a Butterworth digital filter in the Python programming language has been developed, and its verification has been carried out in relation to an audio file. The work of the model is based on the use of Python libraries such as Matplotlib, SciPy and Librosa, which allow you to implement the required algorithm and get the visualization of the signal. Practical significance. The results obtained can later be used as a module of a programmable universal digital signal processing system.

Space integrated network: architectural and technical solutions justifica-tion of the ReshUCube-2 space mission

Space missions using small CubeSat-type spacecraft have become widespread. In this regard, integrated space networks are a promising direction for the development of this industry. In this paper, the architecture of such a network is proposed. It is planned that the first node of this network will be the ReshUCube-2 device. Functional requirements and technical limitations of the described architecture were determined. Based on the requirements, a review and comparative analysis of network protocols and technologies of different levels: physical, channel, network, transport and application. As a result, a network stack is proposed that meets these requirements. The key protocols in the stack were chosen: LoRa, 802.15.4, IPv6, 6LoWPAN, RTL, TCP, UDP and CoAP. Methods of software and hardware implementation of network nodes are proposed. A test bench based on specially developed unified devices is demonstrated, on which it is proposed to work out the functions of network interaction. A test payload board for small spacecraft nodes of the space segment is also shown. The results obtained will be used in the development of future space missions of the Reshetnev Siberian State University. In addition, the results can be useful in the design of the Internet of Things, the Internet of vehicles and similar networks. The results of the work can also serve as a basis for future research in the field of network technologies, digital signal processing, inter-satellite interaction and space information systems.

Development of an intelligent dual-beam gamma densitometer for real-time recognition of two-phase flow regime in horizontal pipe

This work includes the hardware and software development of a high sampling rate dual-beam gamma densitometer for real-time two-phase flow monitoring. The designed densitometer consists of two fast SiPM-based gamma detectors and a custom embedded system for digital signal processing and running flow regime recognition neural network. An exclusive LSTM deep neural network has been developed to classify flow regimes into six classes including stratified, annular, bubbly, wavy, slug, and plug. Therefore, the proposed design is superior to the traditional approaches by (i), unifying signal processing and flow identification units into a single cost-effective embedded system; (ii), reducing the need for time-consuming signal preprocessing steps from conventional to feed-forward neural networks, and (iii), real-time identification of the flow due to the high refresh rate of the data processing chain. The optimal neural network model has been obtained through comprehensive sensitivity analyses to have the best interpolation and generalization. The experimental evaluations showed that the optimized model recognizes the flow regime based on 6 s of gamma data sequence with an accuracy of ∼92%–97% depending on the flow regime in the pipeline. Furthermore, the real-time experiment proved the successful performance of the densitometer to trace the flow regime across the two-phase flow map.

Optimized reverse converters with multibit soft error correction support at 7nm technology

Residue number system (RNS) speeds up digital signal processing systems involving dominant addition and multiplication. Addition and multiplication are accelerated further and performed with a balanced performance on one-hot coded (OHC) residue digits. However, the high complexity of the RNS reverse converter (RC) may kill the performance gain. This paper proposes a high-speed and scalable RNS-RC for both regular and one-hot RNS. For redundant RNS (RRNS), an RRNS-RC is proposed, which based on majority-voting between OHC residue digits, corrects multibit soft errors occurring in a single residue channel. With pass-transistor logic and low-power FinFETs, the proposed RCs are optimized. The simulated RRNS-RC corrected 98.5% of soft errors, while consuming 7, 6.2 and 0.4% of the system's area, leakage power and dynamic power, respectively. As compared to the leading lookup table RC in the literature, RNS-RC exhibited 10.3X, 4.4X and 1.8X savings in area, average power, and delay, respectively.

Computational methods to increase the speed of FPGA-based discrete wavelet transforms

The article considers the computational methods and features of the construction of a complex functional block for the implementation of the discrete wavelet transform (DWT) Dobeshie 9/7 in digital image signal processing systems based on FPGA. We proposed a mathematical model and algorithms for the implementation of parallel and series-convector methods of signal processing to calculate the coefficients of a discrete bi-orthogonal Dobeshie wavelet 9/7 taking into account the architecture of used FPGA. The model is based on wavelet transform factorization methods using lifting schemes. In contrast to conventional lifting schemes, the proposed method and algorithms can increase the speed of FPGA calculations with simplified hardware implementation. CAD Quartus II and ModelSim are used as a development environment. The behavioral model is written in Verilog HDL. Altera Cyclone® IV 4CE115 was used as FPGA. On the basis of the obtained behavioral model the testing module was developed and the simulation of digital circuit in the ModelSim environment was carried out. The formula for estimating the number of clock cycles of the forward and reverse DWT has been proposed; on its basis the estimate of the number of parallel computations depending on the number of input elements and the characteristics of the FPGA was obtained. As a result of experiments the dependences of the number of cycles for DWT computation depending on the size of the side of a square image with different variants of the number of parallel processing blocks were obtained. It is shown that parallel work of several independent modules gives a possibility to conduct concurrent processing of several input columns (rows) from input 2D array, and unification of the multiplier-summing module allows to increase efficiency of calculations and to reduce volume of occupied hardware resources. Conveyor based DWT structure is characterized by less hardware costs in terms of implementation of the calculator unit and memory allocation. As a result of testing the digital circuit, it was found that the developed block structure can significantly increase the DWT speed as well as reduce the cost of the system on a chip. The proposed realization of the block of two-dimensional forward and reverse wavelet transform for the Dobeshi 9/7 filter bank forms a complete module and can be used as a ready-made complex functional block for further development of high quality image transmission systems in real time.

Fast FPGA-Based Multipliers by Constant for Digital Signal Processing Systems

Traditionally, the usual multipliers are used to multiply signals by a constant, but multiplication by a constant can be considered as a special operation requiring the development of specialized multipliers. Different methods are being developed to accelerate multiplications. A large list of methods implement multiplication on a group of bits. The most known one is Booth’s algorithm, which implements two-digit multiplication. We propose a modification of the algorithm for the multiplication by three digits at the same time. This solution reduces the number of partial products and accelerates the operation of the multiplier. The paper presents the results of a comparative analysis of the characteristics of Booth’s algorithm and the proposed algorithm. Additionally, a comparison with built-in FPGA multipliers is illustrated.

ПРИМЕНЕНИЕ ПРОГРАММИРУЕМЫХ ЛОГИЧЕСКИХ ИНТЕГРАЛЬНЫХ СХЕМ В СИСТЕМАХ МНОГОКАНАЛЬНОЙ ЦИФРОВОЙ ОБРАБОТКИ СИГНАЛОВ СПУТНИКОВОЙ НАВИГАЦИИ

The study analyzes multichannel digital satellite navigation signal processing systems for unmanned aerial vehicles. To advance interference insusceptibility of navigation equipment on the basis of adaptive change in settings, it is advisable to apply a field programmable gate arrays in order to implement variations of algorithms of signal processing without reconfiguring the equipment’s structure in changes in radioelectronic settings. A navigation complex with the function of interference insusceptibility is developed based on the field programmable gate arrays. It may simultaneously receive signals from such satellite navigation systems as GLONASS, GPS, QZSS, BeiDou, Galileo, and NavIC via four independently tuned channels and their digital processing using adaptive filtering algorithms. Patterns in spatial selectivity of signals are studied, as are the possibilities for navigation equipment adaptability in interference settings using programs for electrodynamic modeling of adaptive antenna arrays ‒ SolidWorks, Altium Designer, and Quartus.

A real-time phase processing system for phase sensitive optical time domain reflectometer.

In order to improve the real-time performance of a phase-sensitive optical-time-domain reflectometer (Φ-OTDR), a fully digital phase processing system is demonstrated. Using digital down-conversion and field programmable gate array (FPGA) hardware calculation, the phase of the Rayleigh scattering light can be demodulated in real-time. Benefiting from the pipeline calculation in the FPGA, the real-time performance of this system is not affected by the interrogation rate and fiber sensing distance. Experiments show that this real-time detection system has the same vibration detection performance as an offline data process and has good stability. The dynamic strain sensing with a sensing distance of 50 km, an interrogation rate of 1kHz, and a spatial sampling interval of 1m is experimentally demonstrated. The obtained results indicate that the fully digital signal processing system can ensure the real-time detection of Φ-OTDR under the condition of long distance and high resolution.

Hybrid Logic Computing of Binary and Stochastic

Binary logic is applied internally to almost all digital signal processing and computer systems, because binary logic is direct implemented in CMOS circuits. Stochastic logic is achieved through its particular representation of data, which uses the probability of the logic level being ON to represent data. Stochastic logic computing is a type of logic computation based on stochastic bit stream instead of the binary numbers. This letter proposes a hybrid computing system of binary logic and stochastic logic, called hybrid logic. The study discusses how to generate hybrid logic circuits, and demonstrates the properties of hybrid logic circuits.