A Nonlinear Function Logic Computing Architecture With Low Switching Activity

Abstract

Nonlinear functions are widely involved in modern digital signal processing systems, which are usually calculated by polynomial approximation, CORDIC algorithm, or look-up tables. Due to the quite complex logic computing architectures, these methods suffer from high switching activity of logic elements, resulting in tremendous dynamic power consumption. Reducing the switching activity is believed an efficient way to save dynamic power. In this brief, we first analyzed and proved the low switching activity feature of the conventional unary number representation. Afterward, a novel multi-hot unary number representation method and the corresponding logic computing architecture with low switching activity are proposed for nonlinear function, which significantly reduces switching activity and power consumption. Moreover, the proposed nonlinear function logic computing architecture is extended to single input multiple output nonlinear function calculation, which shares the multi-hot encoder to further reduce the hardware cost. According to the post-synthesis power evaluation using PrimePower tools, the proposed architecture achieves significant switching activity and dynamic power reduction compared to conventional computing architectures.