Digital Signal Processing Systems Research Articles

Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory

In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened.

Development of a binocular vision-based catcher robot system using DSP platform

This study adopted the digital signal processing system of Texas instruments as an embedded processing system for a catcher robot. Two cameras were used to capture images, and image processing techniques were applied to calculate the centroid of the target object image. The 3-D coordinates of the target object in space were then calculated according to the principles of binocular vision. The error coming from visual calculation was less than the size of the target object. Next, the Lagrange interpolation formula and a linear equation were used to calculate (in real time) the trajectory of the ball in space and the location to catch the ball. Finally, inverse kinematics was used to control the 2° of freedom robotic arm to catch balls pitched by humans from a distance of 4 m. Combining the advantages of the platform and the hardware efficacy with a processing rate of 30 frames/s, a low-cost rapid robot visual tracking system resembling a human is established.

High-performance and low-energy buffer mapping method for multiprocessor DSP systems

When implementing digital signal processing (DSP) applications onto multiprocessor systems, one significant problem in the viewpoints of performance is the memory wall. In this paper, to help alleviate the memory wall problem, we propose a novel, high-performance buffer mapping policy for SDF-represented DSP applications on bus-based multiprocessor systems that support the shared-memory programming model. The proposed policy exploits the bank concurrency of the DRAM main memory system according to the analysis of hierarchical parallelism. Energy consumption is also a critical parameter, especially in battery-based embedded computing systems. In this paper, we apply a synchronization back-off scheme on the top of the proposed high-performance buffer mapping policy to reduce energy consumption. The energy saving is attained by minimizing the number of non-essential synchronization transactions. We measure throughput and energy consumption on both synthetic and real benchmarks. The simulation results show that the proposed buffer mapping policy is very useful in terms of performance, especially in memory-intensive applications where the total execution time of computational tasks is relatively small compared to that of memory operations. In addition, the proposed synchronization back-off scheme provides a reduction in the number of synchronization transactions without degrading performance, which results in system energy saving.

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool

In the last two decades, many efficient algorithms and architectures have been introduced for the design of low-complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low-complexity MCM operations albeit at the cost of an increased delay. In this paper, we address the problem of optimizing the gate-level area in digit-serial MCM designs and introduce high-level synthesis algorithms, design architectures, and a computer-aided design tool. Experimental results show the efficiency of the proposed optimization algorithms and of the digit-serial MCM architectures in the design of digit-serial MCM operations and finite impulse response filters.

Design and implementation of a digital electrocardiographic system

To work with bioelectrical signals of the human body is not an easy work. It is necessary to know some biological and electric aspects of the human body. This paper describes necessary knowledge and steps for designing and implementing a digital system for acquisition and processing of an electric human body signal: electrocardiographic signal (EKG). Some of the most important aspects to be considered in the implementation of a digital signal processing (DSP) system to work with human bioelectric signals are described: graphic computation, electronic circuits design with real time restrictions, human body electric signals analysis and online algorithms design). In the context of the last two indicated aspects, some algorithms for the signal filtering are described and some improvements to a classic algorithm for QRS detection of an ECG signal are shown.

Digital signal processing system for electromagnetic flowmeter with comb-shaped band-pass fil-ter

Digital signal processing system for electromagnetic flowmeter with comb-shaped band-pass fil-ter

Analysis of influence of sample frequency on quality of formation of quadrature component of analytical signal

Despite the large number of publications on digital signal processing in systems of different appointment, up to date, when choosing the sample frequency of recorded oscillations, their authors refer to the Nyquist’s theorem (sampling theorem). This theorem is connected with the transform of the continuous signal in the sequence of its discrete values. It is assumed that the signal will be transmitted through the band-limited communication channel. However, until now the question of the impact of the frequency on the efficiency of the further digital processing remains open. The article studies the influence of the sample frequency on the efficiency of the digital signal processing applying the method of simulation. The research was performed on the example of formation of the quadrature component of the analytical signal by means of Hilbert and Hilbert-Huang transforms. For the first time we have assessed the quality of the formation of the quadrature component, depending on the sample frequency at various signal/ noise ratios. These results can be used in radio, radar, acoustic and seismic systems of different appointment.

Power Efficient Sum of Absolute Difference Algorithms for video Compression

Video Compression (VC) is one of the resource hungry key element in video communication and is commonly achieved using Motion Estimation (ME). In this paper we proposed power efficient one bit full adder and one of the simple and easy metric called Sum of Absolute Difference (SAD) for estimating the motion vectors in motion estimation. SAD is primarily used to detect motion in the video sub system. Here we proposed power efficient 4X4 and 8X8 SAD architectures. The proposed 4X4 SAD proves that 29%, 63.23% and 61.31% improvement in leakage power, dynamic power and total power respectively as compared with existing 4X4 SAD. Similarly the proposed 8X8 SAD which proves that 57%, 46.16% and 46.78% improvement in Leakage Power (LP), Dynamic Power (DP) and Total Power (TP) respectively as compared with that of existing 8X8 SAD at the gate level. The designs are implemented in ASIC methodology using cadence tools. Keywords - SAD, ME, VC, CSA, DSP, LP, DP, TP, FPGA etc. I. INTRODUCTION Many recent multimedia applications of digital video systems such as video conferencing, video-on- demand, video-phone, distance learning and digital TV, object tracking and many more have become popular products because of their convenience. Such applications require video compression with ever higher compression ratios, better visual quality and high bandwidth. The high efficiency video compression commonly uses the efficient hardware architectures. In general the development of hardware architectures are designed to form the integrated circuits which allows parallel processing of data from various sub blocks of the architectures, however hardware architectures suffers from limitations such as algorithm flexibility due to timing dependencies, which arises from the dataflow of various blocks of the architecture. Thus the development of good architecture of video codec in integrated circuits is very important. The customization of video codec is the video compression in the modern state of the art real time Digital Signal Processing (DSP) systems. Video compression is one of the techniques in video processing system to reduce resource usage. The two primary challenges addressed during video compression are:  Limited Network bandwidth.  Limited Storage capacity. Hence the two important metrics of a video encoder are low computational complexity & low power hardware implementation. Present day world, compression ratio plays the major role in the field of video processing. The motion in the video scene will reduce the efficiency of the compression ratio. Hence the motion estimation field has seen the highest research topic and interested issue in the past a few decades. In short the motion estimation means the estimation of the displacement (or velocity) of image structures from one frame to another in a time sequence of 2-D images of the video in order to achieve video compression in video coding. The efficiency of the compression ratio can be increased by exploiting the similarities between the video frames. The simple metric system is the SAD algorithm, where the absolute differences between the corresponding elements are added up. There are varieties of video coding standards in the video processing systems; the modern video coding standard is H.264/AVC. This coding standard uses the Variable Block Size Motion Estimation (VBSME), in this standard; the computation requirements are much higher than the previous coding standards such as H.263/ MPEG-IV. In H.264/AVC, each picture frame is divided into many macro blocks.

Mechatronic Control System on a Finite-State Machine

This paper describes design using state-transition methodology. This state-transition methodology is straightforward, with a simply-perceived relation between the programming and the corresponding sequential function. The current operational function of the system is described as the current state of the system using state-transition programming. The state transition diagram or table describes the current state and the conditions for transition. The operation is transferred to a corresponding destination state when a set of conditions become valid for leaving the current state. Thus, the sequential operation is explicit, and any continuous conditions scanning (from command source and sensors) only include those that are pertinent for leaving the current state. The methodology is highly-structured and efficient, the programming tasks are readily comprehensible, and fault diagnostics can be easily included within the program's structure. The presented application of an automatic sliding-door illustrates the feasibility of this approach. This paper presents the MFSM (Modular Finite-State Machine), the ECA (Event-Condition-Action) system, motion generation, motion control with load estimation, and an example of a DSP (Digital Signal Processor) system. The limitations and attributes of each technique are discussed, and a state-table format is presented with the capability of representing parallel asynchronous sequential processes.

Design and Implementation of a Multichannel Pulse Compression System Based on FPGA

The implementation of digital signal process system based on FPGA is an important method for embedded system. Pulse compression can be implemented in digital method. The realization of a multichannel pulse compression system by using all digital method has the characteristics of high reliability, strong anti-disturbance, good flexibility and convenient for application. In essence, pulse compress is a method of frequency spectrum expanding, and is used in matched filtering. It incarnates the matching level of filter and the expectant phase of received signal. A multichannel pulse compression system is designed using FFT IP core which can be reused in different periods of digital pulse compression, respectively performing FFT and IFFT calculation, so that the hardware consumption is saved significantly. This paper presents the logic programming of Multichannel Pulse Compression System based on Xilinx FPGA, and introduces the high- speed transmission module, the digital signal process module and the data buffer module in detail.

Implementation of High Speed Modified Booth Multiplier and Accumulator (Mac) Unit

The most effective way to increase the speed a is to reduce the number the partial products because multiplication precedes a series additions for the partial products. To reduce the number calculation steps for the partial products, MBA algorithm has been applied mostly where CSA has taken the role increasing the speed to add the partial products. To increase the speed the MBA algorithm, many parallel multiplication architectures have been researched. A modified booth has been designed which provides a flexible arithmetic capacity and a tradeoff between output precision and power consumption due to using SPST architecture. Moreover, the ineffective circuitry can be efficiently deactivated, thereby reducing power consumption and increasing speed operation. The experimental results have shown that the proposed outperforms the conventional in terms power and speed operation. In this paper we used Xilinx-ISE tool for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification. I. Introduction Fast multipliers are essential parts digital signal processing systems. The speed multiply operation is great importance in digital signal processing as well as in the general purpose processors today, especially since the media processing took off. In the past multiplication was generally implemented via a sequence addition, Subtraction, and shift operations. Multiplication can be considered as a series repeated additions. The number to be added is the multiplicand, the number times that it is added is the multiplier, and the result is the product. Each step addition generates a partial product. In most computers, the operand usually contains the same number bits. When the operands are interpreted as integers, the product is generally twice the length operands in order to preserve the information content. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use positional representation. It is possible to decompose multipliers into two parts. The first part is dedicated to the generation partial products, and the second one collects and adds them. The basic multiplication principle is two fold, i.e. evaluation partial products and accumulation the shifted partial products. It is performed by the successive Additions the columns the shifted partial product matrix. The multiplier is successfully shifted and gates the appropriate bit the multiplicand. The delayed, gated instance the multiplicand must all be in the same column the shifted partial product matrix. They are then added to form the product bit for the particular form. Multiplication is therefore a multi operand operation. To extend the multiplication to both signed and unsigned numbers, a convenient number system would be the representation numbers in twos complement format. Multipliers are key components many high performance such as FIR filters, microprocessors, digital signal processors, etc. A systems performance is generally determined by the performance the because the is generally the slowest clement in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area the is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. As a result, whole spectrums multipliers with different area-speed constraints are designed with fully parallel processing. In between are digit serial multipliers where single digits consisting several bits are operated on. These multipliers have moderate performance in both speed and area. However, existing digit serial multipliers have been plagued by complicated switching and/or irregularities in design. Radix 2^n multipliers which operate on digits in a parallel fashion instead bits bring the pipelining to the digit level and avoid most the above problems. They were introduced by M. K. Ibrahim in 1993. These structures are iterative and modular. The pipelining done at the digit level brings the benefit constant operation speed irrespective the size of the multiplier. The clock speed is only determined by the digit size which is already fixed before the design is implemented. Booth's multiplication algorithm Booth's algorithm can be implemented by repeatedly adding (with ordinary unsigned binary addition) one two predetermined values A and S to a product P, then performing a rightward arithmetic shift on P. Let

Parameterized Scheduling of Topological Patterns in Signal Processing Dataflow Graphs

In recent work, a graphical modeling construct called "topological patterns" has been shown to enable concise representation and direct analysis of repetitive dataflow graph sub-structures in the context of design methods and tools for digital signal processing systems (Sane et al. 2010). In this paper, we present a formal design method for specifying topological patterns and deriving parameterized schedules from such patterns based on a novel schedule model called the scalable schedule tree. The approach represents an important class of parameterized schedule structures in a form that is intuitive for representation and efficient for code generation. Through application case studies involving image processing and wireless communications, we demonstrate our methods for topological pattern representation, scalable schedule tree derivation, and associated dataflow graph code generation.

A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS

Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic and is also commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. While this operation can be readily performed in binary number system, it is extremely difficult to implement in residue number system (RNS). In the absence of an efficient solution to scale an integer directly in residue domain by a programmable power-of-two factor, improvised architecture by cascading fixed RNS scaling-by-two blocks has been previously presented. However, its area complexity and time complexity are worse than a hybrid solution leveraging on binary shifting through efficient residue-to-binary and binary-to-residue conversions. This paper presents a new algorithm for scaling in {2n - 1,2n,2n + 1} RNS by a programmable power-of-two factor. The proposed scaling algorithm breaks the inter-modulus dependency and produces a parallel architecture incurring no more than two logarithmic shifters, one-stage of carry-save adder and a modulo adder in any modulus channel. Comparing with the only available and most efficient hybrid programmable power-of-two scaler for the same moduli set, our proposed design has not only significantly reduced the critical path delay by 52.2%, 52.8%, 53.1%, and 53.2% for n = 5 , 6, 7, and 8, respectively, but also cut down the area by 14.1% on average based on CMOS 0.18 μm standard cell based implementation. In addition, our proposed design has effectively reduced the total power consumption by 43.8% and the leakage power by 20.6% on average.

VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR) filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA) can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW) and clock cycle (ns) of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW) and clock cycle (ns) are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

Development of FPGA-based digital signal processing system for radiation spectroscopy

Abstract We have developed an FPGA-based digital signal processing system that performs both online digital signal filtering and pulse-shape analysis for both particle and gamma-ray spectroscopy. Such functionalities were made possible by a state-of-the-art programmable logic device and system architectures employed. The system performance as measured, for example, in the system dead time and accuracy for pulse-height and rise-time determination, was evaluated with standard alpha- and gamma-ray sources using a CsI(Tl) scintillation detector. It is resulted that the present system has shown its potential application to various radiation-related fields such as particle identification, radiography, and radiation imaging.

A novel signal detection method of giant magneto-impedance magnetic sensors

It is difficult to detect the signal of giant magneto-impedance (GMI) magnetic sensors with the signal-to-noise ratio (SNR) less than 0 dB by the conventional detection methods. In this paper, a novel detection circuit of a GMI sensor is presented, which directly samples the conditioned signals from the GMI sensor into a digital signal processing system and then a hybrid method combining wavelet transform with correlation analysis is proposed, which is proved effective for measuring the weak magnetic field even when the SNR of the GMI sensor signals is as weak as −15 dB.

Integration of Dataflow-Based Heterogeneous Multiprocessor Scheduling Techniques in GNU Radio

As the variety of off-the-shelf processors expands, traditional implementation methods of systems for digital signal processing and communication are no longer adequate to achieve design objectives in a timely manner. There is a necessity for designers to easily track the changes in computing platforms, and apply them efficiently while reusing legacy code and optimized libraries that target specialized features in single processing units. In this context, we propose an integration workflow to schedule and implement Software Defined Radio (SDR) protocols that are developed using the GNU Radio environment on heterogeneous multiprocessor platforms. We show how to utilize Single Instruction Multiple Data (SIMD) units provided in Graphics Processing Units (GPUs) along with vector accelerators implemented in General Purpose Processors (GPPs). We augment a popular SDR framework (i.e, GNU Radio) with a library that seamlessly allows offloading of algorithm kernels mapped to the GPU without changing the original protocol description. Experimental results show how our approach can be used to efficiently explore design spaces for SDR system implementation, and examine the overhead of the integrated backend (software component) library.

A VLSI DSP DESIGN AND IMPLEMENTATION OF COMB FILTER USING UN-FOLDING METHODOLOGY

In signal processing, a comb filter adds a delayed version of a signal to itself, causing constructive and destructive interference. Comb filters are used in a variety of signal processing applications that is Cascaded Integrator-Comb filters, Audio effects, including echo, flanging, and digital waveguide synthesis and various other applications. Comb filter when implemented has lower through-put as the sample period can not be achieved equal to the iteration bound because node computation time of comb filter is larger than the iteration bound. Hence throughput remains less. This paper present the comb filter using one of the methodology needed to design custom or semi custom VLSI circuits named as Un-Folding which increases the throughput of the comb filter. Un-Folding is a transformation technique that can be applied to a DSP program to create a new program describing more than one iteration of the original program. It can unravel hidden con-currency in digital signal processing systems described by DFGs. Therefore, unfolding has been used for the sample period reduction of the comb filter for its higher throughput.

An Efficient VLSI Architecture for FIR Filter using Computation Sharing Multiplier

Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite-impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high-performance applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically doing add and shift operation and also targets computation reuse in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA) can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 4-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method.

An Efficient Design of Vedic Multiplier using new Encoding Scheme

This paper presents a design of efficient Digital Vedic Multiplier using the Vedic sutras from ancient Indian Vedic mathematics. If we are looking towards the signal processing, we will find multipliers and adders plays a very important roll. In fact if we make our focus we can see speed of the Digital signal processing systems is mainly dependent on multipliers and adders. A processor requires more hardware and processing time during multiplication rather than addition and subtraction. In this paper we proposed a new digital Vedic multiplier structure based on a new encoding algorithm. We found that this algorithm reduces the number of partial products so reduces the adders. Thus multiplier is going to faster. In this paper we use Xilinx VHDL module for simulation of Encoder.