Implementation of High Speed Modified Booth Multiplier and Accumulator (Mac) Unit

Abstract

The most effective way to increase the speed a is to reduce the number the partial products because multiplication precedes a series additions for the partial products. To reduce the number calculation steps for the partial products, MBA algorithm has been applied mostly where CSA has taken the role increasing the speed to add the partial products. To increase the speed the MBA algorithm, many parallel multiplication architectures have been researched. A modified booth has been designed which provides a flexible arithmetic capacity and a tradeoff between output precision and power consumption due to using SPST architecture. Moreover, the ineffective circuitry can be efficiently deactivated, thereby reducing power consumption and increasing speed operation. The experimental results have shown that the proposed outperforms the conventional in terms power and speed operation. In this paper we used Xilinx-ISE tool for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification. I. Introduction Fast multipliers are essential parts digital signal processing systems. The speed multiply operation is great importance in digital signal processing as well as in the general purpose processors today, especially since the media processing took off. In the past multiplication was generally implemented via a sequence addition, Subtraction, and shift operations. Multiplication can be considered as a series repeated additions. The number to be added is the multiplicand, the number times that it is added is the multiplier, and the result is the product. Each step addition generates a partial product. In most computers, the operand usually contains the same number bits. When the operands are interpreted as integers, the product is generally twice the length operands in order to preserve the information content. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use positional representation. It is possible to decompose multipliers into two parts. The first part is dedicated to the generation partial products, and the second one collects and adds them. The basic multiplication principle is two fold, i.e. evaluation partial products and accumulation the shifted partial products. It is performed by the successive Additions the columns the shifted partial product matrix. The multiplier is successfully shifted and gates the appropriate bit the multiplicand. The delayed, gated instance the multiplicand must all be in the same column the shifted partial product matrix. They are then added to form the product bit for the particular form. Multiplication is therefore a multi operand operation. To extend the multiplication to both signed and unsigned numbers, a convenient number system would be the representation numbers in twos complement format. Multipliers are key components many high performance such as FIR filters, microprocessors, digital signal processors, etc. A systems performance is generally determined by the performance the because the is generally the slowest clement in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area the is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. As a result, whole spectrums multipliers with different area-speed constraints are designed with fully parallel processing. In between are digit serial multipliers where single digits consisting several bits are operated on. These multipliers have moderate performance in both speed and area. However, existing digit serial multipliers have been plagued by complicated switching and/or irregularities in design. Radix 2^n multipliers which operate on digits in a parallel fashion instead bits bring the pipelining to the digit level and avoid most the above problems. They were introduced by M. K. Ibrahim in 1993. These structures are iterative and modular. The pipelining done at the digit level brings the benefit constant operation speed irrespective the size of the multiplier. The clock speed is only determined by the digit size which is already fixed before the design is implemented. Booth's multiplication algorithm Booth's algorithm can be implemented by repeatedly adding (with ordinary unsigned binary addition) one two predetermined values A and S to a product P, then performing a rightward arithmetic shift on P. Let