Digital Signal Processing Systems Research Articles

Development of a Smart Oriental Medical System Using Security Functions

In future, hospitals are expected to automatically issue remote transcriptions. Many general hospitals are planning to encrypt their medical database to secure personal information as mandated by law. The electronic medical record system, picture archiving communication system, and the clinical data warehouse, amongst others, are the preferred targets for which stronger security is planned. In the near future, medical systems can be assumed to be automated and connected to remote locations, such as rural areas, and islands. Connecting patients who are in remote locations to medical complexes that are usually based in larger cities requires not only automatic processing, but also a certain amount of security in terms of medical data that is of a sensitive and critical nature. Unauthorized access to patients' transcription data could result in the data being modified, with possible lethal results. Hence, personal and sensitive data on telemedicine and medical information systems should be encrypted to protect patients from these risks. Login passwords, personal identification information, and biological information should similarly be protected in a systematic way. This paper proposes the use of electronic acupuncture with a built-in multi-pad, which has the advantage of being able to establish a patient's physical condition, while simultaneously treating the patient with acupuncture. This system implements a sensing pad, amplifier, a small signal drive circuit, and a digital signal processing system, while the use of a built-in fuzzy technique and a control algorithm have been proposed for performing analyses.

Design of Low Voltage High Current DC-DC Converter Based on TPS54810

In digital signal processing system and microcomputer system, often need to high speed DSP devices and large-scale ASIC, FPGA to design and development, in these systems, the high requirement of the precision of the power module and power supply current, power supply module design will directly affect the stability of the whole system. In addition, the power supply module is usually low voltage large current of DC/DC converter, the requirement of efficiency is very high, generally over 90%. This paper introduces the FPGA based on TI company's TPS54810 power supply with low voltage large current DC/DC converter module design, this paper introduces in detail the external compensation of synchronous buck DC/DC converter power supply circuit design methods.

오디오 컨텐츠를 위한 비음수 행렬 분해 기법 기반의 실시간 단일채널 배경 잡음 추출 기법

본 논문에서는 비음수 행렬 분해 (NMF) 기법을 이용하여 단일 채널에서 배경음 성분을 추출하는 알고리즘에 대해 서술한다. 이러한 배경음 성분 추출은 오디오 업믹싱 시스템을 고려하여 개발되었으며, 기존의 연구를 통하여 분리된 배경음 신호가 업믹싱 시스템에 적용될 경우 공간감을 향상시킬 수 있다는 사실이 이미 확인된 바 있다. 다만 기존의 기법은 음향 신호를 모두 축적하여 일괄적으로 처리해야 한다는 단점이 있어, 스트리밍 시스템이나 디지털 시그널 프로세서 (DSP) 등을 이용한 시스템에서 사용되기 어렵다. 본 논문에서는 이를 해소하기 위하여 실시간 비음수 행렬 분해 기법을 이용한 배경음 추출 시스템을 고안하여 실험하였다. 실험에서 처리된 음원을 스펙트럼 평활도를 이용하여 분석한 결과, 고안된 배경음 추출 시스템이 기존의 일괄 추출 시스템과 유사한 정도로 배경음 성분을 추출했음을 확인할 수 있었다. In this paper, monaural ambient component extraction algorithm based on nonnegative matrix factorization (NMF) is described. The ambience component extraction algorithm in this paper is developed for audio upmixing system; Recent researches have shown that they can enhance listener envelopment if the extracted ambient signal is applied into the multichannel audio upmixing system. However, the conventional method stores all of the audio signal and processes all at once, so it cannot be applied to streaming system and digital signal processor (DSP) system. In this paper, the ambient component extraction algorithm based on on-line nonnegative matrix factorization is developed and evaluated to solve the problem. As a result of analysis of the processed signal with spectral flatness measures in the experiment, it was shown that the developed system can extract the ambient signal similarly with the conventional batch process system.

IJARCCE - Computer and Communication Engineering

2 Abstract: The filter whose response to the impulse signal is bounded, popularly known to be the Finite Impulse Response Filter, (shortly an FIR filter) is an important component for designing an efficient digital signal processing system. In different DSP applications FIR filters are widely used. Many applications in digital communication uses the techniques for power reduction are developed particularly in, words processing involving adaptive sound cancelation, seismic signal handing out (noise cancelation), requires large order FIR filters for many other synthesis operations of signal. So, an FIR filter is being constructed, which is efficient in terms of power. Here, the new implementing approach was adopted by the adder and multiplier for designing of FIR filter. The multiplier used is Modified Wallace Multiplier, will reduce the number of partial products. The Carry skip (carry by pass) adder attenuates the unwanted addition and thereby lessening the dissipations of switching power. This paper presents an efficient implementation and analysis for performance evaluation of multiplier and adder to minimize the consumption of power during multiplication and addition by comparing with different adders and multipliers. The proposed design has compact power and improved performance when compared with the proposed FIR filter with comprises of conventional FIR filter. This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx FPGA environment. The result analysis shows that the proposed FIR filter consumes low power than conventional FIR Filter.

CMOS-compatible 2-bit optical spectral quantization scheme using a silicon-nanocrystal-based horizontal slot waveguide.

All-optical analog-to-digital converters based on the third-order nonlinear effects in silicon waveguide are a promising candidate to overcome the limitation of electronic devices and are suitable for photonic integration. In this paper, a 2-bit optical spectral quantization scheme for on-chip all-optical analog-to-digital conversion is proposed. The proposed scheme is realized by filtering the broadened and split spectrum induced by the self-phase modulation effect in a silicon horizontal slot waveguide filled with silicon-nanocrystal. Nonlinear coefficient as high as 8708 W−1/m is obtained because of the tight mode confinement of the horizontal slot waveguide and the high nonlinear refractive index of the silicon-nanocrystal, which provides the enhanced nonlinear interaction and accordingly low power threshold. The results show that a required input peak power level less than 0.4 W can be achieved, along with the 1.98-bit effective-number-of-bit and Gray code output. The proposed scheme can find important applications in on-chip all-optical digital signal processing systems.

IJIREEICE - Electrical, Electronics, Instrumentation and Control

A new architecture, namely, Multiplier-and accumulator (MAC) based Radix-4 Booth Multiplication Algorithm for high-speed arithmetic logics have been proposed and implemented on Xilinx FPGA device. By combining multiplication with accumulation and devising a hybrid type adder the performance was improved. The modified booth encoder will reduce the number of partial products generated by a factor of 2. Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product.

Investigation of the computational efficiency and validity of the surface response to excitation method

The Surface Response to Excitation (SuRE) method excites the surface of the structure with a piezoelectric element. The generated vibrations at critical points on the surface are measured with other piezoelectric elements, a laser vibrometer or other sensors. Then the magnitude of the transfer function between the excitation and the sensory signal is monitored. The performance of the SuRE method was evaluated using a low cost Digital Signal Processor (DSP) system, spectrum analyzer, and laser vibrometer. The accuracies of the Teager–Kaiser (TKA), Goertzel, RMS and average of the positive values algorithms were evaluated for magnitude estimation. The SuRE method was employed successfully for detection of compression loads by using the DSP system. Existence of composite coating was inspected using a spectrum analyzer. Finally, the method was used to detect localized loads on an aluminum plate with a laser vibrometer. The study indicated that the SuRE method may be used as a low cost alternative to impedance method. The inconvenience of using separate sensor(s) is the disadvantages of the SuRE method respect to the impedance method. The main advantages are requirement of simpler and cheaper instrumentation for data analysis, defect location estimation capability when multiple sensors are used, faster data acquisition at low noise environments, and allowing non-contact sensors such as laser vibrometers for measurement of surface response.

DSP Embedded Early Fire Detection Method Using IR Thermal Video

Here we present a simple flame detection method for an infrared (IR) thermal camera based real-time fire surveillance digital signal processor (DSP) system. Infrared thermal cameras are especially advantageous for unattended fire surveillance. All-weather monitoring is possible, regardless of illumination and climate conditions, and the data quantity to be processed is one-third that of color videos. Conventional IR camera-based fire detection methods used mainly pixel-based temporal correlation functions. In the temporal correlation function-based methods, temporal changes in pixel intensity generated by the irregular motion and spreading of the flame pixels are measured using correlation functions. The correlation values of non-flame regions are uniform, but the flame regions have irregular temporal correlation values. To satisfy the requirement of early detection, all fire detection techniques should be practically applied within a very short period of time. The conventional pixel-based correlation function is computationally intensive. In this paper, we propose an IR camera-based simple flame detection algorithm optimized with a compact embedded DSP system to achieve early detection. To reduce the computational load, block-based calculations are used to select the candidate flame region and measure the temporal motion of flames. These functions are used together to obtain the early flame detection algorithm. The proposed simple algorithm was tested to verify the required function and performance in real-time using IR test videos and a real-time DSP system. The findings indicated that the system detected the flames within 5 to 20 seconds, and had a correct flame detection ratio of 100% with an acceptable false detection ratio in video sequence level.

Investigations and Simulations of All optical Switches in linear state Based on Photonic Crystal Directional Coupler

Switching is a principle process in digital computers and signal processing systems. The growth of optical signal processing systems, draws particular attention to design of ultra-fast optical switches. In this paper, All Optical Switches in linear state Based On photonic crystal Directional coupler is analyzed and simulated. Among different methods, the finite difference time domain method (FDTD) is a preferable method and is used. We have studied the application of photonic crystal lattices, the physics of optical switching and photonic crystal Directional coupler. In this paper, Electric field intensity and the power output that are two factors to improve the switching performance and the device efficiency are investigated and simulated. All simulations are performed by COMSOL software.

English

Fast Fourier Transforms (FFT), Discrete Cosine Transforms (DCT) are major blocks in communication systems.FFT is used to compute DFT with reduced number of arithmetic units. The major applications of FFT include signal analysis, image filtering, sound filtering, data compression, partial differential equations etc. The proposed design reports the architecture of 16 point complex FFT core using NEw Distributed Arithmetic (NEDA) algorithm. In order to implement FFT, radix-4 Decimation-In-Time algorithm is used. NEw Distributed Arithmetic is used for complex multiplications. It is one of the techniques used to implement many digital signal processing systems that require multiply and accumulate units. The advantage of the NEDA is that, it is a multiplier-less and ROM- less method and the entire section can be implemented using adders and shifters only, thus minimising the hardware requirement compared to other architectures. In the NEDA section, modified carry select adder with Binary-to-Excess one Converter (BEC) logic is used for addition. The design is simulated by using ModelSim SE(6.2b) and synthesised by Xilinx ISE project navigator(13.2).The synthesis results are taken for different Virtex FPGAs (Virtex 4,Virtex 5,Virtex 6).These results show that the computation for calculating the 16 point FFT is efficient in terms of area and power using the proposed method.

Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing

Parallelization of Digital Signal Processing (DSP) software is an important trend in Multiprocessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as Synchronous Dataflow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra- and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We first address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized are parallel actors (i.e., they can be parallelized to exploit multiple cores). For this special case, we develop and experimentally evaluate a two-phase scheduling framework with three work flows that involve particle swarm optimization (PSO) -- PSO with a mixed integer programming formulation, PSO with simulated annealing, and PSO with a fast heuristic based on list scheduling. Then, we extend our scheduling framework to support the general PAS problem, which considers both parallel actors and sequential actors (actors that cannot be parallelized) in an integrated manner. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions. We also demonstrate the performance of our scheduling framework from two aspects: simulations on a diverse set of randomly generated SDF graphs, and implementations of an image processing application and a software defined radio benchmark on a state-of-the-art multicore DSP platform.

A study on fast digital discrimination of neutron and gamma-ray for improvement neutron emission profile measurement.

Neutron and γ-ray (n-γ) discrimination with a digital signal processing system has been used to measure the neutron emission profile in magnetic confinement fusion devices. However, a sampling rate must be set low to extend the measurement time because the memory storage is limited. Time jitter decreases a discrimination quality due to a low sampling rate. As described in this paper, a new charge comparison method was developed. Furthermore, automatic n-γ discrimination method was examined using a probabilistic approach. Analysis results were investigated using the figure of merit. Results show that the discrimination quality was improved. Automatic discrimination was applied using the EM algorithm and k-means algorithm.

FAST NEURAL NETWORK FOR GENERALIZED TRIGONOMETRIC TRANSFORMATIONS SYNTHESIS

The structure of the fast hardware neural network, based on generalized trigonometric transformations algorithm is developed. The network is appointed for optimal by some given criteria transformation selection and synthesis in adaptive digital signal processing system.

ZERO ROTATION APROACH FOR DROOP IMPROVEMENT IN CASCADED INTEGRATORS COMBFILTER

Cascaded Integrators Comb (CIC) filter is a special class of linear phase FIR filter. It is the most simple decimation filter which does not require multipliers. Due to its simplicity, the CIC filter is usually used in the first stage of decimation. They are used in multi-rate digital signal processing systems which have different applications such as efficient filtering, sub band loading, analogue / digital conversions, audio video signals. However the filter exhibits a high pass band droop which is inacceptable in different application. In this paper, the improvement in pass band droop is done by zero rotation approach.

Reconfigurable and Reusable Mutual Module Based Parameterization Approach for DWT and FFT Algorithm

Goal of this research article is to study and the analysis of a parameterization technique called Common Operator for an embedded digital signal processing system and implementation of that embedded system using a special architecture to achieve better performance. This can be realized by efficient hardware design with reduced area and low-power dissipation which is a significant challenge for embedded systems, particularly in portable devices. The challenge is even more pronounced when DWT and FFT with large transform lengths need to be realized in embedded hardware for several embedded signal processing applications. When it comes to miniaturization or reuse or sharing of the hardware, two Parameterization approaches, viz; the Common Function approach and the Common Operator approach are the effective ones. But in this study, it is proposed a reconfigurable FFT (Fast Fourier Transform) operator using the common operator approach. This operator can be reconfigured to switch from an operator dedicated to compute the FFT to an operator which computes the FFT in order to perform DWT. Contribution of this study is to Minimize the waste of resources by modifying slightly the FFT butterfly to support the DWT computation and to reduce the resources allocated to the reconfiguration, Simplify the reconfiguration between the two algorithms, by separating the calculation of the Real and Imaginary parts of FFT modules.

Research on DSP Embedded Digital Signal Processing System for Ship Navigation Radar

Development of digital signal processing and embedded technologies today, to the development of radar technology has brought new opportunities. Relative to the simulation of radar, digital radar has good performance, features, ease of operation, and other benefits. Design based on embedded processor and digital signal processor (DSP) dual processor shipboard navigation radar system, and focuses on digital shipborne navigational radar system architecture, hardware design and software algorithms for digital signal processing module, gives the overall scheme for DSP systems.

Digital devices signal processing system based on K-valued differential calculus

The proposed modeling system, based on the K-valued differential calculus provides more qualitative and accurate modeling compared with binary modeling. This is achieved by taking into account the steepness of fronts, amplitude K-valued signal level quantization and considering electromagnetic compatibility during modeling. Modeling in the system is performed by a joint solution of ordinary K-valued differential equations and K-valued delay differential equations. When solving ordinary K-valued differential equations, crosstalk and noise, associated with the electromagnetic compatibility of individual blocks are modeled based on solving ordinary K-valued differential equations. Modeling of the functional blocks of logic elements is carried out based on the K-valued delay differential equations. The joint solution of these two types of equations allows to analyze the performance of high-speed computing devices, designed taking into account the steepness of fronts, as well as races and noise, caused by electromagnetic interaction of individual components

FPGA–DSP co-processing for feature tracking in smart video sensors

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

POWER EFFICIENT AND HIGH THROUGHPUT OF FIR FILTER USING BLOCK LEAST MEAN SQUARE ALGORITHM IN FPGA

In silicon on chip technology demands high performance and low power Very Large Scale Integrated Circuit (VLSI) digital signal processing (DSP) systems. The aim of this paper explores the power consumption technique for the architecture of Finite Impulse Response (FIR) adaptive filter. An adaptive FIR filter with Block Least Mean Square (BLMS) algorithm was developed to reduce the power. Distributed arithmetic (DA)-based formulation of BLMS algorithm is used to reduce the area where both convolution operation to compute filter output and correlation operation to compute weight-increment term could be performed by using the same LUT. Thus a DA based implementation of adaptive filter is highly computational and area efficient.

20-Bit RISC and DSP System Design in an FPGA

These days, most microprocessor and microcontroller designs are based on a Reduced Instruction Set Computer (RISC) core, and many operations - such as discrete cosine transform (DCT), inverse DCT, discrete Fourier transform (DFT), and fast Fourier transform (FFT)--are performed by a digital signal processor (DSP) system. Here, the authors present the design of a RISC and DSP system that uses very high-density logic (VHDL) and a field-programmable gate array (FPGA). This RISC is a 20-bit processor.