IJARCCE - Computer and Communication Engineering

Abstract

2 Abstract: The filter whose response to the impulse signal is bounded, popularly known to be the Finite Impulse Response Filter, (shortly an FIR filter) is an important component for designing an efficient digital signal processing system. In different DSP applications FIR filters are widely used. Many applications in digital communication uses the techniques for power reduction are developed particularly in, words processing involving adaptive sound cancelation, seismic signal handing out (noise cancelation), requires large order FIR filters for many other synthesis operations of signal. So, an FIR filter is being constructed, which is efficient in terms of power. Here, the new implementing approach was adopted by the adder and multiplier for designing of FIR filter. The multiplier used is Modified Wallace Multiplier, will reduce the number of partial products. The Carry skip (carry by pass) adder attenuates the unwanted addition and thereby lessening the dissipations of switching power. This paper presents an efficient implementation and analysis for performance evaluation of multiplier and adder to minimize the consumption of power during multiplication and addition by comparing with different adders and multipliers. The proposed design has compact power and improved performance when compared with the proposed FIR filter with comprises of conventional FIR filter. This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx FPGA environment. The result analysis shows that the proposed FIR filter consumes low power than conventional FIR Filter.