Design and Implementation of FPGA based Low Power Digital FIR Filter

Abstract

Abstract : Finite impulse response (FIR) filters are widely used in various DSP applications. The low-power or low-area techniques developed specifically for digital filters can be found in. Many applications in digital communication (channel equalization, frequency channelization), speech processing (adaptive noise cancelation), seismic signal processing (noise elimination), and several other areas of signal processing require large order FIR filters ,since the number of multiply - accumulate (MAC) operations required per filter output increases linearly with th e filter order, real - time implementation of these filters of large orders is a challenging task. This paper presents the methods to reduce dynamic power consumption of a digital Finite Impulse Response (FIR) filter these methods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to fir filters to power consumption reduced thus reduce power consumption due to glitches is also reduced. This paper is implemented using XILINX ISE and hardware used is Spartan-3E and family is XC2S200E.