Digital Signal Processing Block Research Articles

Hybrid ALM-DSP TDC in Intel Arria 10 FPGA

The article presents the first implementation of a time-to-digital converter (TDC) using a digital signal processing (DSP) block from an Intel field-programmable gate array (FPGA) device. The design and configuration capabilities of the DSP blocks of the leading FPGA manufacturers, AMD and Intel, are compared in the context of time/digital conversion. Next, three variants of TDCs are presented. The problem of ultra-wide bins observed in both the classic version of the converter based on the Adaptive Logic Modules (ALM) and the version built using only DSP blocks has been mitigated in a hybrid variant, combining both solutions. The proposed variant of the hybrid ALM-DSP TDC implemented in Arria 10 FPGA from Intel (20 nm process node) achieved a resolution of 2.1 ps, a single-shot-precision better than 6.36 ps and reduced the maximum differential nonlinearity (DNL) error from 74.5 ps to 12.7 ps.

Sub-rate sampled, non-integer fractionally spaced Volterra nonlinear equalizer for IM/DD systems

As high-speed analog-to-digital converters (ADC) account for a significant portion of the receiver’s cost in intensity-modulation (IM)/direct-detection (DD) systems, there have been substantial efforts to employ an ADC operating at a relatively low sampling rate. However, half-symbol-spaced electronic nonlinear equalizers used to compensate for nonlinear waveform distortions commonly operate at 2 samples/symbols, and thus require digital upsampling before the equalization. This implies that the digital signal processing (DSP) at the receiver should also operate at 2 sample/symbol even though the ADC operates at the sub-rate (i.e., < 2 sample/symbol). Hence, we propose and experimentally demonstrate the sub-rate sampled, non-integer fractionally spaced Volterra nonlinear equalizer (VNLE). This equalizer does not require the digital upsampling, and thus makes the entire receiver DSP block operating at the sub-rate, the same as the sampling rate of ADC. We estimate the complexity of the proposed equalizer by the number of multipliers required for its implementation. We also evaluate the performance of the proposed VNLE over a 64-Gb/s 4-ary pulse amplitude modulation link and compare the performance with the conventional VNLE (requiring digital upsampling). The results show that the proposed VNLE incurs a very slight performance degradation compared with the conventional VNLE, but reduces the implementation complexity considerably since it obviates the need for digital upsampling at the receiver.

Design and Implementation of a Cost‐Effective, Portable Impedance Analyzer Device with AD5941

This study proposes a cost‐effective, small‐size, and portable impedance analyzer using the AD5941 Analog Front End (AFE) that makes frequency sweep measurement for various applications. The design utilizes a microcontroller and an AD5941 circuit for impedance measurement. The AD541 is a high precision impedance converter system that consists of a 16‐bit, 1.6 MSPS, analog to digital converter (ADC), an integrated waveform generator, and a digital signal processing (DSP) block. The AD5941 has many advantages over the AD5933 which was used in numerous studies in the past decade. Also, the device implements the four‐wire impedance method which is an impedance measuring technique that reduces the effect of electrodes to achieve higher accuracy. A supporting Graphic User Interface (GUI) software is employed to control the Impedance Analyzer device and to visualize the measurement. This impedance analyzer achieves a frequency resolution of 0.015 Hz and can generate sinusoid up to 200 kHz. In frequency range from 10 kHz to 150 kHz, the device can measure impedance in the range of 10 Ω–100 kΩ with less than 4.3% of error in comparison with benchtop impedance analyzer, Microtest 6632. Moreover, our impedance measurement device has undergone testing involving human calf measurements and electrochemical quantification, particularly for estimating Sodium Chlorite. The experimental outcomes demonstrate that our design not only fulfills the criteria of an impedance analyzer device but also performs effectively across diverse applications. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic

The purpose of the paper is to propose a new implementation of the PID (proportional–integral–derivative) algorithm in digital hardware. The proposed structure is optimized for cost. It follows a serialized, rather than parallel, scheme. It uses only one arithmetic block, performing the multiply-and-add operation. The calculations are carried out in a sequentially cyclic manner. The proposed circuit operates on standard single-precision (32-bit) floating-point numbers. It implements an extended PID formula, containing a non-ideal derivative component, and weighting coefficients, which enable reducing the influence of setpoint changes in the proportional and derivative components. The circuit was implemented in a Cyclone V FPGA (Field-Programmable Gate Array) device from Intel, Santa Clara, CA, USA. The proper operation of the circuit was verified in a simulation. For the specific implementation, which is reported in the paper, the sampling period of 516 ns was obtained, which means that the proposed solution is comparable in terms of speed with other hardware implementations of the PID algorithm operating on single-precision floating-point numbers. However, the presented solution is much more efficient in terms of cost. It uses 1173 LUT (Look-up Table) blocks, 1026 registers, and 1 DSP (Digital Signal Processing) block, i.e., about 30% of logic resources required by comparable solutions.

Simultaneous reception of AMCC signals and QPSK signals by a single coherent receiver with DSP.

This paper investigates an auxiliary management and control channel (AMCC) signal extraction method using digital signal processing (DSP) blocks with 3-step moving averaging that allows a single coherent receiver to receive main signal and AMCC signal simultaneously. Receiver sensitivity characteristics versus the modulation index (MI) and average number of the proposed DSP blocks are elucidated. Based on the results, we discuss a policy for designing the parameters. Experiments apply the design policy to achieve receiver sensitivity of -41.8 dBm with both 25 Gbit/s QPSK main signal and 128 kbit/s AMCC signal; the main signal sensitivity penalty is just 0.2 dB.

Small Logarithmic Floating-Point Multiplier Based on FPGA and Its Application on MobileNet

The small floating-point (SFP) multiplier proposed by Xilinx is utilized to implement the convolution neural networks (CNNs). This scheme can balance the resource usage of look-up tables (LUTs) and digital signal processing blocks (DSPs) so that high compute density is achieved on Field Programmable Gate Arrays (FPGAs). In addition, this scheme can quantize the CNNs with several simple scaling operations rather than a lengthy compute intensive retraining process. However, the mantissa field of SFP multiplier is required to be less than or equal to 3-bit, thus significantly restricts the application of this scheme. To figure out this issue, we implement the SFP multiplier in the logarithmic domain such that the multiplication is performed by the addition with the aid of logarithmic and anti-logarithmic converters that is referred to as small logarithmic floating-point (SLFP) multiplier. Compared to SFP multiplier (3-bit mantissa), the proposed SLFP multiplier can support multiple accuracy levels ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\mathbf {\mathrm {\sim }}5$ </tex-math></inline-formula> -bit mantissa) with a relatively low overhead ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0\mathbf {\mathrm {\sim }} 3\mathbf {\times }$ </tex-math></inline-formula> LUT6s). Moreover, we utilize the look-ahead carry chain to reduce the delay of addition so that the proposed SLFP multiplier can operate at 650MHz. As a result, the latency (1.5ns, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\mathbf {\times }$ </tex-math></inline-formula> clock cycle) and throughput (650MOPS) of proposed SLFP multiplier ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\mathbf {\mathrm {\sim }}5$ </tex-math></inline-formula> -bit mantissa) are the same as the SFP multiplier (3-bit mantissa). In the end, the implementation of MobileNet proves that the accuracy level of SFP multiplier (3-bit mantissa) is not sufficient, which can be solved by the proposed SLFP multipliers (5-bit mantissa).

Реализация блока формирования сигналов на основе динамической системы Лоренца на программируемых логических интегральных схемах

The implementation of the generation unit of direct-chaotic signals based on the dynamic Lorentz system for a field programmable gate array is described in this article. The unit was designed for generating wide-band chaotic signals for “real-time” systems. The calculation of the Lorentz nonlinear dynamic system is carried out in the formats with floating point and the half-precision fixed point. The main task goal is optimization and minimization of using the digital signal processing blocks of field programmable gate array crystal. A comparative analysis of the realization of the generation unit for required resources with the realization based on the floating point in the format and the half-precision fixed point format which is also described in this article

Vibration Detection and Localization Using Modified Digital Coherent Telecom Transponders

We demonstrate a vibration detection and localization scheme based on bidirectional transmission of telecom signals with digital coherent detection at the receivers. Optical phase is extracted from the digital signal processing blocks of the coherent receiver, from which the vibration component is extracted by bandpass filtering, and the position along the cable closest to the vibration's epicenter is recovered by correlation. We demonstrate our scheme first using offline experiment with 200-Gb/s DP-16QAM, and we report field trial results over installed fiber to detect real-world vibration events.

The Wave-Union Method on DSP Blocks: Improving FPGA-Based TDC Resolutions by 3x With a 1.5x Area Increase

Achieving high-resolution time-to-digital conversion is challenging at high count rates. In past work, the highest resolutions with low dead times (≤2 cycles) on field-programmable gate arrays (FPGAs) have been achieved using digital signal processing (DSP) blocks or using the wave-union method. In this article, we investigate the possibility of combining the wave-union method with DSP blocks. With the given configuration on a Xilinx Artix-7 200T FPGA, we achieve 13.60-ps single-shot precision (SSP) using only 3.78% of the FPGA fabric per channel (1.22% of the fabric in the finite step response (FSR) injector and 2.56% of the fabric in the delay line) for three edges, compared to 52.65 ps using 2.97% of the FPGA fabric per channel without the wave-union method. The scaling of edge numbers (for higher resolutions) is shown to be significantly better than the previously suggested parallel implementation, at just 0.407% of the FPGA fabric per edge compared to ~2.5% per edge in the parallel implementation. Temperature characterization showed an SSP penalty of just 4 ps over a 60 °C temperature difference.

Design of DCO-OFDM System for VLC on Chip at the Register-Transfer Level

This paper reports a System-on-Chip (SoC) architecture design for the DC-biased optical OFDM (DCO-OFDM) Visible Light Communication (VLC) transceiver. The proposed SoC comprises several Digital Signal Processing (DSP) blocks, i.e., Fast Fourier Transform (FFT), Convolutional Encoder (CE), Viterbi Decoder, Quadrature Phase-Shift Keying (QPSK) Modulator/Demodulator, Interleaver/Deinterleaver, and Synchronizer. System was designed through the combination of two Intellectual Property (IP) types: designing IP from the scratch (custom-based IP) and employing available core accelerator IP served by the third party, which is Xilinx library (reuse-based IP). All DSP blocks were targeted for the FPGA development board (Xilinx Zynq SoC 7000), then combined with the ARM microprocessor. In this study, ARM microprocessors were used for various tasks, i.e., scheduling process, on-chip memory as a temporary data storage function, Analog-to-Digital Converter (A/D), Digital-to-Analog Converter (D/A), and Ethernet module as communication medium between SoCs and personal computer (PC). Testing was carried out on the Register Transfer Level (RTL) for hardware (H/W) and software (S/W) models implemented on ARM microprocessors. The system performances were measured through the point-to-point data communication scenarios between a PC transmitter and PC receiver. A 77 kbps of data communication speed and 2.9 ms of data processing latency were obtained using 100 MHz clock speed. The VLC on-chip was successfully demonstrated in RTL phase. This system is suitable for a low-rate communication system application, generally for joint VLC and Internet-things (IoT) technology, (then called as VLC/IoT).

The SALT-Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment.

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit

Convolutional neural networks (CNNs) are widely used in modern applications for their versatility and high classification accuracy. Field-programmable gate arrays (FPGAs) are considered to be suitable platforms for CNNs based on their high performance, rapid development, and reconfigurability. Although many studies have proposed methods for implementing high-performance CNN accelerators on FPGAs using optimized data types and algorithm transformations, accelerators can be optimized further by investigating more efficient uses of FPGA resources. In this paper, we propose an FPGA-based CNN accelerator using multiple approximate accumulation units based on a fixed-point data type. We implemented the LeNet-5 CNN architecture, which performs classification of handwritten digits using the MNIST handwritten digit dataset. The proposed accelerator was implemented, using a high-level synthesis tool on a Xilinx FPGA. The proposed accelerator applies an optimized fixed-point data type and loop parallelization to improve performance. Approximate operation units are implemented using FPGA logic resources instead of high-precision digital signal processing (DSP) blocks, which are inefficient for low-precision data. Our accelerator model achieves 66% less memory usage and approximately 50% reduced network latency, compared to a floating point design and its resource utilization is optimized to use 78% fewer DSP blocks, compared to general fixed-point designs.

Combined Neural Network and Adaptive DSP Training for Long-Haul Optical Communications

Machine Learning (ML) algorithms have shown to complement standard digital signal processing (DSP) tools in mitigating fiber nonlinearity and improving long-haul transmission performance. However, dynamic transmission impairments such as polarization effects and carrier phase noise corrupt the training data and conventional cost functions for neural network (NN) training become unsuitable. Simple cascade of ML and standard adaptive DSP blocks will also result in suboptimal transmission performance or require impractical training methodologies in presence of such dynamic transmission impairments. We show how the adaptive DSP blocks can be treated as extra stateful NN layers and be combined with the main NN so that standard backpropagation-like training algorithms in ML can be applied. In this case, the adaptive filters are viewed as NN states which are updated in the forward pass of the backpropagation. We study the combined training of linear and nonlinear parameters in the digital backpropagation (DBP) algorithm for fiber nonlinearity compensation (named generalized DBP (GDBP) hereafter), residual impairments, polarization effects, frequency offsets and carrier phase noise compensation filters as a single NN in a 7 × 288 Gb/s polarization multiplexed (PM)-16QAM transmission experiment over 1125 km. We derived the complete set of backpropagation-like gradients and state update equations for the static and dynamic parameters of the combined NN. We further proposed and open-sourced a JAX-based coding framework for their easy and practical implementation. GDBP is more generalized than other DBP variants proposed in literature and for a given total number of steps, GDBP is the first experimental demonstration of optimal single-channel DBP based-fiber nonlinearity compensation algorithm. In addition, for complexity constrained situations with shortened filter taps, GDBP enables a 1 dB performance improvement over other DBP variants.

Cost-effective and robust DSP scheme for a short-reach coherent system in the presence of transmitter IQ skew and chromatic dispersion.

A cost-effective and robust digital signal processing (DSP) scheme is proposed and demonstrated experimentally in a coherent 61 GBaud PDM 16QAM system. In our scheme, multi-stage DSP blocks are used to deal with channel effects, transceiver in-phase and quadrature (IQ) skew, and phase noise. A 4×4 real-valued multiple-input multiple-output (RV-MIMO) with N1 taps is for polarization recovery and receiver IQ skew calibration. After frequency offset compensation, two 2×2 RV-MIMO with N2 taps are used to compensate for chromatic dispersion (CD), inter-symbol interference, transmitter IQ skew, and phase noise. Finally, the residual phase noise is eliminated by the maximum likelihood (ML) estimator. The experimental results indicate that the proposed scheme provides better received optical power sensitivity and CD tolerance than the existing simplified DSP schemes. In addition, the proposed scheme can tolerate transmitter IQ skew up to 7 ps in a 10 km case, which outperforms both simplified and conventional DSP schemes. Meanwhile, the proposed scheme can keep the same transceiver IQ skew and CD tolerance and has reduced complexity by 25% after 10 km links, compared to 4×4 RV-MIMO followed by a transmitter skew compensator. To the best of our knowledge, the proposed scheme is the most cost-effective solution for a high baud rate datacenter interconnects where transmitter IQ skew and CD have to be dealt with.

Inverse Hyperbolic Tangent Fiber for OAM Mode/Mode-Group Division Multiplexing Optical Networks

A novel weakly guiding multimode fiber (MMF) with enhanced performance, named inverse hyperbolic tangent MMF (IHTAN MMF), is proposed and designed to exhibit larger separation ( ≥ 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> -4</sup> ) within 14 mode groups (MGs). This ensures improved available data channels compared with standard graded-index MMF and various recent orbital angular momentum (OAM) fibers, thus enabling a transmission free of multiple-input/multiple-output (MIMO). A numerical study of the key characteristics and performance metrics of the proposed IHTAN MMF is performed. The modal analysis shows a large separation between the supported MGs, thereby enabling low inter-channel crosstalk (XT) and enhanced OAM mode purities (99.9%). Consequently, resistivity to intrinsic XT is enhanced (-30 dB). Low differential intergroup and intragroup delays and flat and low chromatic dispersion are analyzed (proved), discussed, and compared with those of recent fibers. Comparison findings show that IHTAN MMF could play a role in short- or medium-haul MG multiplexing communications free of MIMO digital signal processing (DSP). Finally, the multiplexing, transmission, and demultiplexing system of 50 OAM data channels collocated with small, cost-effective, energy-efficient MIMO DSP blocks are discussed to enhance the scalability of the proposed fiber. The results show that IHTAN MMF could be a promising candidate for next-generation MMF-enabled OAM transmission systems.

Design and analysis of high performance and low power FFT for DSP datapath using Vedic Multipliers

ABSTRACT Fast Fourier Transform is one of the most efficient methods of performing computation in Digital signal processing blocks. These computations are basically performed by the inherent floating-point multiplier units residing inside the butterfly units of any FFT. To optimise an FFT for higher efficiency and performance, it is inevitable to use highly efficient adder and multiplier units within the datapath architecture of a FFT processor. This work proposes high-performance FFT units designed using optimised Vedic multiplier units for DSP processor cores. Choice of Vedic multiplier decreases power and delay overheads of design which leads to production of an efficient FFT. A comparative analysis is presented for 24-bit Vedic multiplier using nine adder variants. A separate analysis of inherent adders is also done. Using the two best proposed Vedic multipliers, FFT units of 8, 16 and 64-point are designed respectively. The designed FFT units are compared for dynamic power, area and delay with existing designs and an analysis is presented. Power efficiency of nearly 25% and delay efficiency of around 50% is achieved with respect to the existing designs. The design is simulated on Virtex-7 FPGA using Verilog HDL.

Digital-to-time converter for test equipment implemented using FPGA DSP blocks

This paper presents a novel digital-to-time converter (DTC) implemented using digital signal processing (DSP) blocks built in field-programmable gate array (FPGA) devices. The converter was implemented in a low-cost Xilinx Spartan-6 FPGA chip manufactured in the 45 nm CMOS process and can be applied in any other programmable logic device that contains DSP blocks. The designed DTC time interval jitter is below 2.8 ps. This is the lowest time interval jitter so far reported in such kind of circuits implemented in a programable device. The obtained resolution of up to 8.6 ps is about twice as good as that achieved in a single carry-chain-based delay-line. Furthermore, the designed circuit saves FPGA general-purpose logic (programmable logic blocks). This kind of converter can be especially useful as a part of test instrumentations as well as time-domain signal processing systems implemented in the latest generation of programmable logic devices.

Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs.

Due to the huge success and rapid development of convolutional neural networks (CNNs), there is a growing demand for hardware accelerators that accommodate a variety of CNNs to improve their inference latency and energy efficiency, in order to enable their deployment in real-time applications. Among popular platforms, field-programmable gate arrays (FPGAs) have been widely adopted for CNN acceleration because of their capability to provide superior energy efficiency and low-latency processing, while supporting high reconfigurability, making them favorable for accelerating rapidly evolving CNN algorithms. This article introduces a highly customized streaming hardware architecture that focuses on improving the compute efficiency for streaming applications by providing full-stack acceleration of CNNs on FPGAs. The proposed accelerator maps most computational functions, that is, convolutional and deconvolutional layers into a singular unified module, and implements the residual and concatenative connections between the functions with high efficiency, to support the inference of mainstream CNNs with different topologies. This architecture is further optimized through exploiting different levels of parallelism, layer fusion, and fully leveraging digital signal processing blocks (DSPs). The proposed accelerator has been implemented on Intel's Arria 10 GX1150 hardware and evaluated with a wide range of benchmark models. The results demonstrate a high performance of over 1.3 TOP/s of throughput, up to 97% of compute [multiply-accumulate (MAC)] efficiency, which outperforms the state-of-the-art FPGA accelerators.

Fault Tolerant Digital Data-Path Design via Control Feedback Loops

In this paper, we propose a novel fault tolerant methodology for digital pipelined data-paths called Control Feedback Loop Error Decimation (CFLED), that reduces the error magnitude at the outputs. The data-path is regarded from a control perspective as a process affected by perturbations or faults. Based on the corresponding dynamic model, we design feedback control loops with the goal of attenuating the effect of the faults on the output. The correction loops apply correction factors to selected data-path registers from blocks that have their execution rewinded. We apply the proposed methodology on the data-path of a controller designed for a 2-degree of freedom robot arm, and compare the cost and reliability to the generic triple modular redundancy. For Field Programmable Gate Array (FPGA) technology, the solution we propose uses 30% less slices with respect to Triple Modular Redundancy (TMR), while having a third less digital signal processing blocks. Simulation results show that our approach improves the reliability and error detection.

Cooperative wideband spectrum sensing in cognitive radio based on sparse real‐valued fast Fourier transform

The Cognitive Radio (CR) plays a key role in identifying free bandwidths in the Radio Frequency (RF) spectrum. High-speed Analog-to-Digital Converters are normally applied for spectrum sensing of sideband signals providing several raw data for digital signal processors resulted in energy-inefficient complex circuits and hardware resources in digital signal processing blocks. In some instances, the frequency spectrum is sparsely occupied by various users, i.e., only a few active frequency bands exist at the same time. This feature enables CR application to use sub-Nyquist sampling approaches for designing a system representing significantly reduced cost and power consumption, as well as improved processing speed. The current paper introduced a novel Cooperative Real-valued Sparse Spread Spectrum Sensing algorithm (CR4S) based on a sub-Nyquist sampling approach by employing the sparsity of the frequency spectrum and the real-valued properties of the RF signal to identify free bandwidth with minimum computational complexity. The CR4S algorithm aimed at improving CR spectrum sensing by utilizing techniques such as Real-valued FFT, Sparse Fast Fourier Transform, and collaborative spectrum sensing. The proposed algorithm has been approved by simulation to above 95% detection performance. The performance enhancement in the CR4S algorithm is an emerging advance being fascinating for portable CR devices.