Abstract
SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.
Highlights
The Large Hadron√ Collider (LHC) provides proton–proton collisions, at the centre of mass energies up to s = 13 TeV, which are studied by four large experiments: ATLAS [1], CMS [2], Large Hadron Collider beauty (LHCb) [3], and ALICE [4]
These results verify the performance of the chip, they are not sufficient to qualify a complete detector system
Detailed measurements of the complete detector setup quantifying chip parameters on different hybrids will be presented in future publications
Summary
New Physics phenomena may be studied via direct searches (production of new particles) or indirect ones where we concentrate on precise measurements of selected observables and compare the results with the Standard Model predictions. In both scenarios, the task of discovering. New Physics requires, for instance, very precise and robust tracking systems that are able to provide a momentum measurement with very high resolution (typically better than one percent). This in turn, sets stringent demands on the quality and functionality of the readout electronics. To conform with higher luminosity and the fully softwarebased trigger, all sub-detectors require front-end electronics that provide readout at the LHC bunch-crossing rate of 40 MHz [6]
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