Abstract
In this paper, we propose a novel fault tolerant methodology for digital pipelined data-paths called Control Feedback Loop Error Decimation (CFLED), that reduces the error magnitude at the outputs. The data-path is regarded from a control perspective as a process affected by perturbations or faults. Based on the corresponding dynamic model, we design feedback control loops with the goal of attenuating the effect of the faults on the output. The correction loops apply correction factors to selected data-path registers from blocks that have their execution rewinded. We apply the proposed methodology on the data-path of a controller designed for a 2-degree of freedom robot arm, and compare the cost and reliability to the generic triple modular redundancy. For Field Programmable Gate Array (FPGA) technology, the solution we propose uses 30% less slices with respect to Triple Modular Redundancy (TMR), while having a third less digital signal processing blocks. Simulation results show that our approach improves the reliability and error detection.
Highlights
Reliability represents a key factor in electronic devices that operate in radiation prone environments, frequent in applications in the aerospace domain
This indicates that the number of erroneous results is higher in the case of Control Feedback Loop Error Decimation (CFLED), the error magnitudes achieved with the proposed method are lower compared to Triple Modular Redundancy (TMR)
Virtex-7 VX485T-2 Field Programmable Gate Array (FPGA) device, using the Xilinx Vivado 2017.1 tool are depicted in Table 4 for the baseline—non-fault tolerant—circuit, and the controlled, fault tolerant version, with two CFLED enhanced circuits providing the reference to the other
Summary
Reliability represents a key factor in electronic devices that operate in radiation prone environments, frequent in applications in the aerospace domain. Redundant residue number systems have been employed for signal processing data-paths in [13,14]; in this case, modular redundancy is employed, with each replica having its own residue representation Another approach uses a design inspired from the Markov Random Field (MRF) theory. Different from all the mentioned approaches, this work proposes a control engineering approach—Control Feedback Loop Error Decimation (CFLED)—for improving the reliability of digital data-path processing pipelines, by employing feedback control loops to reduce the error magnitude. The considered use case consists of a processing pipeline that relies on function evaluations—performed using Taylor series—scalar-matrix multiplications, and vector-matrix multiplications Such operations are widely used in applications such as graphic processing and signal and image processing.
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