Synthesizing optimal registerfile architectures for FPGA technology

Abstract

This paper presents for the first time an optimization approach to synthesis of application-specific registerfile architectures which are targeted for field programmable gate array (FPGA) technologies. A new integer programming (IP) model is presented that supports simultaneous scheduling, binding, and allocation, to minimize the number of registerfiles and the interconnect complexity (or the number of tristate drivers and multiplexor inputs). The TP model is used to map an application to a registerfile architecture suitable for prototyping or implementation in user-programmable FPGA technologies, such as Xilinx 4000. The same model supports early transferring of data on busses, and at most one registerfile is connected to each bus. Application-specific architectures with fewer busses, fewer registerfiles and up to 34% fewer bus connections than previous research have been synthesized. These IP synthesized architectures have also been successfully implemented in Xilinx 4000 FPGA technology to verify the approach. This research breaks new ground by (1) simultaneously scheduling, binding, and allocating registerfile architectures in practical cpu times, (2) synthesizing architectures which are suitable for prototyping or implementing in user-programmable FPGA technologies and (3) providing industry with a DA tool for synthesizing architectures with low interconnect complexity. >