Digital Signal Processing Applications Research Articles

Design of Multipliers Using Various Methods

Multipliers are highly on demand as they are used in tremendous areas such as digital signal processing applications, image processing application , and in various Microprocessors such as ARM, NVIDIA, Intel, DSP Processors such as DM270,DM320 etc. Many researchers are urging to improve the performance of the multipliers by adopting various methods. Most of the existing papers includes the work on Array multipliers, Wallace tree multiplier, Dadda multiplier and Booth multipliers. And few recent papers include Vedic Mathematics that have implemented most commonly used Urdhva Sutra. In this paper, various methods are implemented to design a multiplier such as Booth multiplier, Modified Booth multiplier, Urdhva multiplier and Nikhilam multiplier. All the methods are used to design for 8bit signed numbers by coding very efficiently in Verilog. This paper focuses on the design of multipliers that are very simple in structure such that there is no circuit complexity. The design is simulated using Xilinx ISE or ModelSim SE.

A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics

The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.

Design and Implementation of a 32-bit Floating Point Unit

A Floating Point Unit is a math co-processor that is in the most demand of Digital Signal Processing (DSP), Processors and more. It is used to perform functions or operations on floating point numbers like addition, subtraction, multiplication, division, square root and more. It is specifically designed to carry out mathematical operations and it can be emulated in CPU. Floating point unit is a common operation used in advanced Digital Signal Processing and various processor applications. The aim was to develop an optimized floating point unit so that the delay was reduced and efficiency was increased. The floating point unit has been written according to IEEE 754 standard and the entire design has been coded in Verilog HDL. The results are improved by 12% with the usage of Vedic multiplier that is a delay of 4.450ns as compared to 5.123ns with an array multiplier. Designs can be further optimized using low power designing techniques at architectural level. Different behaviour can be observed for different size and technologies.

Design of High-Speed Low Power Computational Blocks for DSP Processors

In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

An Efficient Reverse Converter for the Four Non Coprime Moduli Set {2n,2n-1,2n-2,2n-3}

In this paper, residue to binary conversion is presented for the four moduli setsharing a common factor. A new and efficient converter for the moduli set using multipliers, carry saves and modular adders is proposed based on a cyclic jump approach. A theoretical hardware implementation and comparison with a state-of- the- art scheme showed that the proposed scheme performed better. The 4- moduli set selected provides a larger dynamic range which is needed for Digital Signal Processing (DSP) applications [7].

Resourceful Fast Discrete Hartley Transform to Replace Discrete Fourier Transform with Implementation of DHT Algorithm for VLSI Architecture

Discrete Fourier Transform (DFT) is used in a range of digital signal processing applications, such as signal and image compression systems, filter banks, signal representation or harmonic analysis. The Discrete Hartley Transform (DHT) can be used to effectively replace the DFT when the input sequence is real. This paper introduces and applies the Discrete Hartley Transform (DHT) algorithm, which is well suited to the VLSI architecture. The purpose of using the DHT algorithm is to reduce the complexity of the VLSI architecture. With the introduction of VLSI architectures, 100,000 transistors can be mounted on a single chip. For manufacturers, the verification of these circuits on breadboards is not feasible. Computer-aided design methods have now come into being, but programmers also had to make connections manually at the gate level. Subsequently, Hardware Description Language (HDL) such as Verilog and VHDL came into being. With the integration of the DHT algorithm and its execution, Verilog authors have worked to reduce the complexity of the VLSI circuits in this article. With reduced complexity, the power consumption is reduced and thus the area is therefore reduced. DHT is an algorithm for the Radix-2. It is especially useful for image and signal processing. The DHT algorithm for length N=8 is introduced here.

Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform

For the overall performance of systems like microprocessors and digital signal processors (DSPs) platforms, arithmetic units, all must be efficient in terms of speed, power, and area. Multipliers and dividers are inevitable hardware employed in such systems. This paper focuses on Vedic mathematics algorithms for multiplication and division for power-efficient, faster, and area-efficient design. For four- and eight-bit Vedic multiplication algorithms, Urdhva Tiryagbhyam and Nikhilam Sutras are employed in this paper. For eight-bit Vedic division algorithms, Nikhilam and Dhwajank Sutras are used. The Vedic mathematics algorithms are also compared to conventional methods of multiplication (like Array multiplier) and division (using Booth multiplication algorithm). As an application of DSP, the linear convolution operation is implemented using both conventional and Vedic algorithms. It has been observed that the Vedic algorithms operate faster, consume less power, and occupy less area on a targeted hardware platform. The implementations were carried out using the Verilog HDL language and Xilinx’s Vivado EDA tool. To measure various performance parameters, Cadence simvision (using 180-nm GPDK CMOS Technology) and Xilinx’s ISE tool were also used.

Design and Analysis of Multiplier Using High Speed Adders

In all digital signal processing (DSP) applications like FFT, digital filters the main problem faced by processor is its propagation delay. Every high speed signal processing is depends on multiplier circuits. Multiplier performance is directly influenced by the adder design. In this paper, we design low power and high speed carry look ahead (CLA) adder for multiplier circuit by using multi value logic (MVL) based on quaternary signed digits (QSD). The ability of multi value logic (MVL) circuits to achieve more information density and high operating speed when compared to that of existing binary circuits is highly impressive. MVL circuits have attracted important attention for the design of digital systems. Based on quaternary signed digits, the carry look ahead adder is designed, implemented in multiplier circuit and simulated by using cadence virtuoso design suite by 180nF technology.

A compact hybrid dielectric resonator antenna for multiband in wireless applications

This article exhibits the composite dielectric resonator antenna (DRA) for ISM band, Wi-Max and WLAN applications. The proposed DRA is aiming for speech signal and video transmission in the range of wi-max/WLAN. DRA’s are used in many digital signal processing applications because they are capable of locating signal sources. Microstrip feed line excites the exhibited structure. A circular dielectric resonator antenna with circular ring and cross shaped strip is designed to generate tri-band characteristics. The proposed antenna structure cover three different frequency bands, i.e. 1.85–2.5 GHz, 2.97–3.92 GHz and 4.821–5.9 GHz, with the fractional bandwidth of 30.1%, 27.5% and 20.9% respectively. An ISM band, Wi-max as well as WLAN are being utilized for correspondence of continuous traffic including speech signal, video and information to supervise medical issues in wireless body area networks (WBAN) advancement. To strengthen the resonator appearance as well as miniaturize the volume, the customized circular metallic component and cross shaped strip are stacked onto the substrate. The simulated results are verified by using fabricated antenna and the results are compared. The proposed model is strongly encouraging the wireless applications.

FPGA Implementation of Proficient 16-Tap FIR Filter Design Using Decision Tree Algorithm

Lately, channel is one of the key components in signal handling applications. Among different channels, Finite Impulse Response (FIR) channel is broadly utilized in Digital Signal Processing (DSP) applications for shifting/denoising. For enormous scope coordination (VLSI) execution of fixed-coefficient FIR channels, huge asset used customary multipliers that can be acknowledged by a solitary steady multiplication (SCM) and numerous consistent augmentations (MCM) square utilizing movement and include/take away tasks. For a proficient execution, a variable size apportioning approach is proposed in direct structure channel structure that devours less zone and 11% of decrease in basic way delay, 40% decrease of all out force utilization, 15% decrease of zone delay product(ADP), 52% decrease of vitality delay product(EDP), and 42% decrease of intensity territory product(PAP), on a normal, over the cutting edge techniques. In this paper, a state choice tree calculation is proposed to decrease unpredictability in channel tap cells of variable size apportioning approach. The proposed plot creates a choice tree to perform move and expansion/deduction and aggregation dependent on the consolidated SCM/MCM approach. This plan diminishes the quantity of postpone registers required for tab cells. The proposed snake design will be actualized in Xilinx Zed, Spartan and Virtex devices and Area, power and speed investigation will be performed.

FPGA Implementation of Data Flow Graphs for Digital Signal Processing Applications

A rapid growth in digital signal processing applications has increased the requirement for high-speed digital systems. Multiprocessor systems are the best choice for these applications. A prior sequence of operations should be applied to the operations that described the nature of these applications before hardware implementation is produced. These operations should be scheduled and hardware allocated. This paper proposes a new scheduling technique for digital signal processing (DSP) applications has been represented by data flow graphs (DFGs). In addition, hardware allocation is implemented in the form of embedded system. A proposed scheduling technique also achieves the optimal scheduling of a DFG at design time. The optimality criteria considered in this algorithm are the maximum throughput within the available hardware resources. The maximum throughput is achieved by arranging the DFG nodes according to their inter-related data dependencies. Then, two nodes can be clustered into one compound task to reduce the overall execution time by minimizing the number of tasks to be executed that minimizing the number of cycles to execute them. Then each task is presented in form of instruction to be executed in the hardware system. A hardware system is composed of one or multiple homogenous pipelined processing elements and it is designed to meet the maximum-rate schedule. Two implementations are proposed of the system architecture according to the number of the processing elements, namely: the serial system and the parallel system. The serial system comprises one processing element where all tasks are processed sequentially, whilst the parallel system has four processing elements to execute tasks concurrently. These systems consist mainly of seven units: central shared memory, state table, multiway function unit buffer, execution array, processing element/s, instruction buffer and the address generation unit. The hardware components were built on an FPGA chip using Verilog HDL. In synthesis results, the parallel system has better system performance by 25.5% than the serial system. While the serial system requires smaller area size, which described by the number of slice registers and the number of the slice lookup tables (LUTs) than the parallel one. The relationship between the number of instructions that are executed in both systems, and the system area and the system performance that presented by system frequency, are studied. By increasing memories size in both systems, the system performance isn’t affected as in a serial system, and it is slightly decreased as the parallel system by 1.5% to 4.5%. In terms of the systems area, both serial system area and parallel system area are increased and in some cases are doubled. The proposed scheduling technique is shown to outperform the retaining technique, which we have chosen to compare with. The serial system has better performance by 19.3% higher system frequency than a retiming technique. And the parallel system also outperforms the retaining technique by 51.2% higher system frequency in synthesis results.

FPGA Implementation of Proficient 16-Tap FIR Filter Design Using Decision Tree Algorithm

Lately, channel is one of the key components in signal handling applications. Among different channels, Finite Impulse Response (FIR) channel is broadly utilized in Digital Signal Processing (DSP) applications for shifting/denoising. For enormous scope coordination (VLSI) execution of fixed-coefficient FIR channels, huge asset used customary multipliers that can be acknowledged by a solitary steady multiplication (SCM) and numerous consistent augmentations (MCM) square utilizing movement and include/take away tasks. For a proficient execution, a variable size apportioning approach is proposed in direct structure channel structure that devours less zone and 11% of decrease in basic way delay, 40% decrease of all out force utilization, 15% decrease of zone delay product(ADP), 52% decrease of vitality delay product(EDP), and 42% decrease of intensity territory product(PAP), on a normal, over the cutting edge techniques. In this paper, a state choice tree calculation is proposed to decrease unpredictability in channel tap cells of variable size apportioning approach. The proposed plot creates a choice tree to perform move and expansion/deduction and aggregation dependent on the consolidated SCM/MCM approach. This plan diminishes the quantity of postpone registers required for tab cells. The proposed snake design will be actualized in Xilinx Zed, Spartan and Virtex devices and Area, power and speed investigation will be performed

Pipeline Architecture for N=K*2L Bit Modular ALU: Case study between current generation computing and Vedic computing

This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using ‘2L’ as base modules using ‘K’ modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU. The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

Pipeline Architecture for N=K*2L Bit Modular ALU: Case study between current generation computing and Vedic computing

This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using ‘2L’ as base modules using ‘K’ modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU. The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}

Magnitude comparison, sign detection and overflow detection are essential operations of residue number system (RNS) that are used in digital signal processing (DSP) applications. Moreover, sign detection attracts significant attention in RNS as it can also be used in division and magnitude comparison operations. However, these operations are not easy to perform in RNS. So, there is a need arise to propose a computationally advanced RNS based sign detector. This paper presents an area and power-efficient sign detection circuit for modulo {2<sup>n </sup>- 1, 2<sup>n</sup>, 2<sup>n</sup> + 1} using mixed radix conversion technique. The proposed sign detector is constructed using a carry save adder (CSA), a modified parallel prefix adder and a carry-generation circuit. Based on the synthesized results using synopsys design compiler, the introduced design offers better results in terms of the area required and power consumption. Although, the speed will remain the same when compared to the recent sign detectors for the same moduli set.

Code-size-aware Scheduling of Synchronous Dataflow Graphs on Multicore Systems

Synchronous dataflow graphs are widely used to model digital signal processing and multimedia applications. Self-timed execution is an efficient methodology for the analysis and scheduling of synchronous dataflow graphs. In this article, we propose a communication-aware self-timed execution approach to solve the problem of scheduling synchronous dataflow graphs on multicore systems with communication delays. Based on this communication-aware self-timed execution approach, four communication-aware scheduling algorithms are proposed using different allocation rules. Furthermore, a code-size-aware mapping heuristic is proposed and jointly used with a proposed scheduling algorithm to reduce the code size of SDFGs on multicore systems. The proposed scheduling algorithms are experimentally evaluated and found to perform better than existing algorithms in terms of throughput and runtime for several applications. The experiments also show that the proposed code-size-aware mapping approach can achieve significant code size reduction with limited throughput degradation in most cases.

Formal verification of Matrix based MATLAB models using interactive theorem proving.

MATLAB is a software based analysis environment that supports a high-level programing language and is widely used to model and analyze systems in various domains of engineering and sciences. Traditionally, the analysis of MATLAB models is done using simulation and debugging/testing frameworks. These methods provide limited coverage due to their inherent incompleteness. Formal verification can overcome these limitations, but developing the formal models of the underlying MATLAB models is a very challenging and time-consuming task, especially in the case of higher-order-logic models. To facilitate this process, we present a library of higher-order-logic functions corresponding to the commonly used matrix functions of MATLAB as well as a translator that allows automatic conversion of MATLAB models to higher-order logic. The formal models can then be formally verified in an interactive theorem prover. For illustrating the usefulness of the proposed library and approach, we present the formal analysis of a Finite Impulse Response (FIR) filter, which is quite commonly used in digital signal processing applications, within the sound core of the HOL Light theorem prover.

Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications

In this work, we proposed a novel Coordinate Rotation DIgital Computer (CORDIC) rotator algorithm that converges faster by performing radix-2,4 and 16 CORDIC iterations while maintaining the scale factor implicitly constant. A mixed-radix is used to achieve convergence faster to reduce the computational latency of the CORDIC algorithm. The main concern of the higher radix CORDIC algorithm is the compensation of a variable scale factor. To solve this problem, the Taylor series approximation of sine and cosine is proposed for a higher radix CORDIC algorithm to achieve the scaling-free rotation of the two-dimensional vector. The scaling-free rotation of the proposed CORDIC algorithm removes the read-only memory (ROM) needed to store scale factor of higher radix CORDIC algorithm. Further, the proposed CORDIC algorithm is designed in rotation mode and optimized by removing the Z datapath for the digital signal processing (DSP) applications for which the angle of rotation is known in advance. Finally, the multipath delay commutator (MDC) fast Fourier transform (FFT) algorithm is implemented with the proposed CORDIC algorithm based rotator on FPGA. The proposed design is compared with existing designs. In a comparison between the radix-16 CORDIC rotator based FFT implementation and our proposed implementation, it has been found out that implementation proposed in this article has used 17% fewer resources.

Design of High Speed and Low Power Approximate Multiplier for Image and Digital Signal Processing Applications

Truncation based approximate multiplier is a scalable multiplier in which truncation is performed based on the leading one bit positions in each and every input operands, hence the number of partial products are reduced. In this multiplier design the multiplication process is done by addition, shifting and multiplication processes which has a very good improvement in space occupation and power consumption when compared to the exact multiplier. To enhance the multipliers speed each and every input operand in the multiplication side are truncated using the method given below. Based upon the leading 1’s the input operands, the inputs are truncated show that the accuracy does not depend on input operand’s width. Hence this multiplier is scalable. Very large improvement in multiplier’s design parameters like power and area consumption are obtained which is independent of the width of the input operand. To find the working efficiency of this multiplier we have compared the design parameters with some recently proposed multipliers and the exact multiplier. They obtained result states that the proposed multiplier enhances power consumption, delay and area up to 90%, 80% and 95% when compared to be exact multiplier. Also our design outsmarts other multipliers in parameters like power consumption, speed and area. Proposed approximate multiplier has zero mean value Gaussian distribution. We have figured it out it by MATLAB applications and a good PSNR and MSE is obtained. The output shows that the degradation in quality is almost negligible. Also we recommend Truncation based approximate multiplier where power consumption has to be adjusted in multiplication operation.

Design of 32-bit cell-based carry-save combinational multiplier with reduced area and propagation delay

In Very Large Scale Integrated (VLSI) and Digital Signal Processing (DSP) applications, a Conventional Combinational Multiplier uses a lot of hardware and propagation delay, and that is one of the main issues. The delay is determined by the ripple carries between the adders. Most techniques used in the combinational multiplier depend on the paper-and-pencil shift-and-add (PPSA) algorithm, which uses ripple carry adder architecture. This paper proposes an architecture called Cell-based Carry-Save Combinational Multiplier (CCCM) that focuses on the propagation delay and area. Each row represents a carry-save adder. The carry outputs are passed to the next row. For validating the proposed architecture, 16x16 multiplication is performed and the overall improvement in the delay is 73.32 % while there is a 3.31 % reduction in the area.