Digital Signal Processing Applications Research Articles

Design and Analysis of High Speed Multiply and Accumulation Unit for Digital Signal Processing Applications

Unit for Digital Signal Processing Applications
 
 Kausar Jahan1, Pala Kalyani2, V Satya Sai3, GRK Prasad4, Syed Inthiyaz5, Sk Hasane Ahammad6
 1Department of ECE, Dadi Institute of Engineering and Technology
 Anakapalle, Andhra Pradesh, India
 2Department of ECE, Vardhaman College of Engineering
 Kacharam, Shamshabad, India
 3Department of ECE, Koneru Lakshmaiah Education Foundation
 Guntur, India-522502
 4Department of ECE, Koneru Lakshmaiah Education Foundation
 Guntur, India-522502
 5Department of ECE, Koneru Lakshmaiah Education Foundation
 Guntur, India-522502
 6Department of ECE, Koneru Lakshmaiah Education Foundation
 Guntur, India-522502
 
 Abstract—The fundamental component used in many of the Digital signal Processing (DSP) applications are Multiply and Accumulation Unit (MAC). In the literature, a multiplier consists of greater number of full adders and half adder in partial product reduction stage, which increases the hardware complexity and critical path delay to MAC unit. To overcome this problem, two novel multipliers are proposed in this article. The proposed multipliers are designed and implemented in hardware, which reduces the circuit complexity and improves the overall performance of the MAC unit with less delay. The proposed multipliers are compared with the 4-bit existing designs and observed that the number of slices Look Up Tables (LUTs) are minimized from 113 to 43, Slices are reduced from 46 to 14, Full Adders (FAs) are lessened from 28 to 23, bonded Input Output Blocks (IOBs) and Half Adders (HAs) were not altered. The time delay is reduced from 14.251ns to 7.876ns. The proposed multipliers are compared in the literature with the 8-bit multiplier, then the number of Slice LUTs are reduced from 510 to 231, Slices are reduced from 218 to 113, FAs are reduced from 120 to 110, HAs are reduced from 56 to 39, time delay is reduced from 26.228ns to12.748ns, but bonded IOBs count remains same. The synthesis and simulations results are verified by using Xilinx ISE 14.7 version tool.

Implementation of non-equal-partition multi-channel convolver

Convolution has become a largely exploited signal operation thanks to his several applications in digital signal processing. In the realm of audio elaboration, convolution has the particular meaning of imposing a spectral and/or temporal structure onto a sound. These structures are completely given by the signal with which the signal is being convolved, called Impulse Response (IR). These signals contain a sort of acoustical footprint that can be completely transferred to another sound, earning the same acoustic characteristics as a consequence. With a multichannel approach, convolution assumes even a further meaning and a wider application field. Indeed, it's exploited to deal with modern spatial sound techniques such as Ambisonics which necessitate matrix elaborations of the involved signals. Ambisonics recordings, for example, are made by special coincident multi-capsule microphone arrays, whose signals can be converted to standard Ambisonics format by a multi-channel convolver. A similar concept can apply to the mixing stage of audio production, where direction-based audio objects must be converted to the Ambisonics format to be reproduced in the relative speaker setups. The aim of the work is to analyse an existing algorithm of a multichannel convolver software evaluating his efficiency. Moreover, the managing of the matrix of filters has showed weaknesses when assembling new matrices. Solution proposes a handy way to deal with matrices and to improve the efficiency of the algorithm.

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

AbstractReversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today’s modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged. Hence, in this paper, it is proposed that the DWT method can be implemented on a field-programmable gate array in a digital architecture (FPGA-DA). We examined the effects of quantization on DWT performance in classification problems to demonstrate its reliability concerning fixed-point math implementations. The Advanced Encryption Standard (AES) algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks (ANN) method. By reducing hardware area by 57%, the proposed system has a higher throughput rate of 88.72%, reliability analysis of 95.5% compared to the other standard methods.

Оптимизация алгоритма деления чисел в системе остаточных классов на основе функции ядра Акушского

Residue number systems find wide application in cryptography, digital and image signal processing, and other domains necessitating division operations. Nevertheless, division is the most computationally intensive activity in residue number systems. An optimized division algorithm based on the Akushsky core function is presented in this paper. The suggested method exhibits superior computational efficiency when compared to the conventional iterative division.

Physical Design of 64-bit Multiplier and Accumulator (MAC) Unit Using Vedic Multiplier and CLA Adder

In digital signal processing, communication systems and many other applications, multiplier and accumulator units play a crucial role. This work presents an overview of 64-bit MAC Unit, where Vedic multiplier is used as multiplier unit and compared Carry select adders (CSA) and Carry look-ahead adder (CLA) which must be used for adder unit, accumulator unit consist of Parallel in parallel out (PIPO) shift registers. As a result, CLA adder to be more effective in terms of lower delay by comparing with other adders. The MAC Unit was modelled using Verilog-HDL, where its functional verification and synthesized was done using Intel Quartus Prime 21.1, which was simulated on Questa Intel FPGA 21.1. Further GDSII file was created using the cadence tool with the help of Incisive for functional simulation, Genus for synthesis and pre-layout timing analysis, and innovus for physical design. Entire study was carried out in 180nm technology from RTL-GDSII. The delay, power, area was monitored, the memory usage, Pre-Clock Tree Synthesis, Post-Clock Tree Synthesis (CTS) were noted before and after optimization of design.

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in a one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool. Classification of an artificial neural network using the iris dataset is carried out in this designed RISC processor. In order to compare the performance, the same artificial neural network is executed in real time within the dual-core ARM Cortex-A9 processor in the operating system of the Zynq-7000 SoC. The results show that the RISC processor designed in the FPGA executes at 20x less clock cycles and 3x higher speed compared to the ARM processor.

Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module

The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems arise when using a multiplier in the realms of area, power, complexity, and speed. This paper details a more efficient MAC (Multiply- Accumulate) multiplier that has been tuned for space usage. The proposed design is more efficient, takes up less room, and has lower latency than conventional designs. The performance of the Additive Multiply Module (AMM) multiplier is measured against that of existing multipliers, where it serves as a module in the MAC reducing area and delay.

A Novel Approach for Polyphase Filter Bank Design Using ABC Algorithm

Polyphase filter banks (PFBs) are the most preferred multirate structures for subband coding in Digital Signal Processing (DSP) and communication. For PFB design, there are many important design parameters such as filter length and frequency selectivity. Also, to realize the desired frequency response in designs, stopband and passband attenuation are of considerable importance. In PFB design, researchers and practitioners frequently use iterative and meta-heuristic optimization methods. Heuristic techniques have a significant problem-solving ability in continuous and discrete solution space. Therefore, they give better results than other suggested methods, and their performance depends on the control parameters. In this study, Artificial Bee Colony (ABC) algorithm was employed for suggested design problem of PFB. In the first stage, the control parameters of the ABC algorithm were examined to improve the performance of the proposed PFB problem. In the second stage, the analysis was carried out by changing filter lengths (8-256) and filter band frequencies (0.3-0.7/0.4-0.6). All results obtained were also compared with the Particle Swarm Optimization algorithm (PSO) and the Genetic algorithm (GA). Finally, a DSP application of PFB was carried out according to best results achieved by the ABC algorithm for filter lengths and frequencies.

Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology

Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a multi-stage carry propagation adder (MSCPA). The simulation demonstrated that the suggested DST-Radix-4 booth multiplier (DST-R4BM) resulted in higher performance in comparison to traditional multiplies in terms of area, delay, and power.

Power Minimization by Designing Novel Architecture for Multimodal Biometric System

Abstract: The reduction of power, area, and delay parameters are increasing as the range of sophistication of applications in VLSI circuit designs. Adders and multipliers play a vital role in VLSI circuit designs to minimize the power consumed by the circuit. The Finite Impulse Response Filter is widely used in Digital Signal Processing Applications, such as speech processing, loudspeaker equalization, echo cancellation, noise cancellation, arithmetic computations and, image-processing applications. In FIR filter, the adders and multipliers are the important components to reduce the power, delay and area. Therefore, this proposed method faced with more constraints: as minimal power as possible. This work proposes a design of low power Finite Impulse Response Filter using Carry Skip Adder.The recent electronics industry uses digital filters for various real time applications. A novel VLSI architecture is designed by using ALU based FIR filters for biometric system. Where in ALU includes adders and multipliers, comparing different adders for there better performance with respect to power and identifying carry skip adder will consume less power compared to other adders. power consumption of overall architecture by including carry skip adder is very less and we can use this same adder for multimodal architecture also.

Inner Product Computation In-Memory Using Distributed Arithmetic

In-memory computing using emerging technologies such as Resistive Random-Access Memory (ReRAM) has been proposed as a promising substitute for future computing applications to address the ‘von Neumann bottleneck’. Multiplication is the key component for inner product computation in every digital signal processing (DSP) application and the complexity of multipliers increases greatly with bit-width. Distributed arithmetic (DA) using look-up tables and adder-shifter module has been proposed for inner product computation to achieve multiplier-less efficient DSP architectures, particularly when one of the vectors is a constant and known in advance. Due to the memory wall, DA can be made furthermore latency and energy-efficient when implemented ‘in memory’. In this work, for the first time, we propose two design techniques to compute inner product completely in memory using DA. This is accomplished by storing the precomputed look-up table contents in a ReRAM array and implementing adder-shifter module also in the same array. The adder-shifter is implemented in memory using majority gates which are in turn realized as READ operations in the memory array. Two methods of mapping: latency-optimized and area-optimized and their comparison in terms of latency and area are presented. The proposed method-1 achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 60$ </tex-math></inline-formula> % energy savings compared to CMOS and the proposed method-2 achieves 10.59 times higher throughput compared to CMOS.

A New Method for Image Protection Using Periodic Haar Piecewise-Linear Transform and Watermarking Technique.

The paper presents a novel data-embedding method based on the Periodic Haar Piecewise-Linear (PHL) transform. The theoretical background behind the PHL transform concept is introduced. The proposed watermarking method assumes embedding hidden information in the PHL transform domain using the luminance channel of the original image. The watermark is embedded by modifying the coefficients with relatively low values. The proposed method was verified based on the measurement of the visual quality of an image with a watermark with respect to the length of the embedded information. In addition, the bit error rate (BER) is also considered for different sizes of a watermark. Furthermore, a method for the detection of image manipulation is presented. The elaborated technique seems to be suitable for applications in digital signal and image processing where high imperceptibility and low BER are required, and information security is of high importance. In particular, this method can be applied in systems where the sensitive data is transmitted or stored and needs to be protected appropriately (e.g., in medical image processing).

ARM CORTEX-M3 MİKRODENETLEYİCİ KULLANIMI İLE ÇOK TAŞIYICILI GÖRÜNÜR IŞIK HABERLEŞME SİSTEMİ GELİŞTİRİLMESİ

With the development of technology, the constraints and the needs in the field of communication have increased. Especially, limited and licensed radio frequencies that can cause electromagnetic interference and health problems in the use of wireless communication make the visible light communication (VLC) technologies very important. In this study, an ARM based VLC system design has been realized to implement a unique product with the use of low-cost and commercial off-the-shelf electronic components. In this context, receiver and transmitter circuits are designed, printed circuit boards and appropriate enclosures have been produced, as a result, a system prototype has been created to use in interior applications with standard ceiling height. The design is also one of the few implementations in which orthogonal frequency division multiplexing (OFDM) modulation and digital signal processing applications are performed by using ARM based microcontroller. Consequently, the system communication is achieved at a data rate of 3.5 kbps from a distance 1.8 m to 3 m. Also the system communication is successfully performed from the center of the light source up to 85 cm distance on the direct side and up to an angle of 50° on the azimuth.

SPEECH EMOTION RECOGNITION

Speech Emotion Recognition, abbreviated as SER, is the act of attempting to recognize human emotion and affective states from speech. This is capitalizing on the fact that voice often reflects underlying emotion through tone and pitch. This is also the phenomenon that animals like dogs and horses employ to be able to understand human emotion. SER is tough because emotions are subjective and annotating audio is challenging.The main objective of this SER, recognizing the emotional state of the speaker from his/her speaker. Various emotions like happiness, sadness, anger, etc. can be recognized. SER uses speech processing to recognize the emotional state. Speech Processing is one of the important branches of digital signal processing and finds applications in Humancomputer interfaces, Telecommunication, Assistive technologies, Audio mining, Security, and so on. Speech Emotion Recognition is important to have a natural interaction between human beings and machines. In SER, the emotional state of a speaker is extracted from his/her speech. The acoustic characteristic of the speech signal is Feature. Feature extraction is the process that extracts a small amount of data from the speech signal that can later be used to represent each speaker. Many feature extraction methods are available and Mel Frequency Cepstral Coefficient (MFCC) is the commonly used method. In this project, speaker emotions are recognized using the data extracted from the speaker's voice signal. Mel Frequency Cepstral Coefficient (MFCC) technique is used to recognize the emotion of a speaker from their voice.

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Multiplication is one of the most basic processes, in digital signal processing applications. To process the instructions, most processors require multiplication. Because multipliers are employed in almost all arithmetic operations, they consume the majority of time and power. As a nutshell, the multiplier's efficiency is critical in terms of enhancing processor performance. The array multiplier is one of the most efficient multipliers since it is both quick and simple. However, power consumption is high. The basic components of an array multiplier are adders. The multiplier's efficiency will improve if the adders are much more efficient. The prior study used Complementary Metal Oxide Semiconductor (CMOS) to construct a Quaternary Carry-Lookahead Adder (CLA) that substitutes the adder circuit in the array multiplier. Quaternary number system circuits are quicker than binary number system circuits and can execute arithmetic operations without carry. However, Quaternary circuits take up more space. As a solution, the Quaternary Carry Increment Adder (CIA) is proposed. The proposed adder consumes less power and occupies less area than the existing Quaternary CLA. In the array multiplier, the Quaternary CIA substitutes the Quaternary CLA. This helps to lower the multiplier's power and area consumption. Tanner EDA tool is used to designing the circuits and were simulated with 180 nm technology. Various parameters such as delay, power and power-delay product of the existing and the proposed are measured and compared.

An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform

Quantum-dot cellular automata (QCA) is a domain coupling nano-technology that has drawn significant attention for less power consumption, area, and design overhead. It is able to achieve a high speed over the CMOS technology. Recently, the tendency to design reversible circuits has been expanding because of the reduction in energy dissipation. Hence, the QCA is a crucial candidate for reversible circuits in nano-technology. On the other hand, the addition operator is also considered one of the primary operations in digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, full-adders have become popular and extensively solve mathematical problems more efficiently and faster. They are one of the essential fundamental circuits in most digital processing circuits. Therefore, this article first suggests a novel reversible block called the RF-adder block. Then, an effective reversible adder design is proposed using the recommended reversible RF-adder block. The QCAPro and QCADesigner 2.0.3 tools were employed to assess the effectiveness of the suggested reversible full-adder. The outcomes of energy dissipation for the proposed circuit compared to the best previous structure at three different tunneling energy levels indicate a reduction in the power consumption by 45.55%, 38.82%, and 34.62%, respectively.

Teaching redundant residue number system for electronics and computer students

This paper describes a study for teaching number system in a computer arithmetic course and addresses the existing gap in the current course by focusing on the characteristics of applications. A redundant residue number system (RRNS) is an efficient and innovative number system that inherits the interesting properties of both residue number system (RNS) and redundant number systems. It breaks the operands into residues by considering a moduli-set and then signifies the residues by a redundant representation. So, by limiting the carry propagation chain inside and outside the moduli, RRNS proposes more efficient arithmetic units which could be employed in digital signal processing (DSP) applications. Despite the applicability of RRNS, there is not well-organized teaching on RRNS covering the recent achievements. Besides, there is an important question for students and researchers what is the most appropriate number representation for each application category? In this paper, we present a step-by-step education process for RRNS that includes basic concepts of RNS and the redundant number system. Then we address characteristics of different applications that RRNS is suitable to be employed for them. So, the method gives a well-organized proceeding to computer arithmetic designers and students.

Parallel Hardware Implementation of Walsh Hadamard Transform

The Walsh Hadamard Transform is a powerful notion in digital signal processing. This paper explains the construction of parallel hardware architecture using the mathematical concept of Kronecker product based approach to Walsh Hadamard Transform and its simulation using Verilog. This architecture is simulated here using Field Programmable Gate Array (FPGA) technology in Verilog Spartan 3e platform. Furthermore, this paper illustrates the fast algorithm and parallel computational result of both one-dimensional and two-dimensional transforms using the Kronecker product.This algorithm can be used to implement a systolic array based dedicated hardware for computation of the transform. Our proposed hardware design for the Walsh Hadamard Transform will be used in various digital signal processing applications. The systematic derivation of parallel architecture design using the concept of Kronecker product and stride permutation would depict the real time processing rather than conventional way and reducing time complexity using minimal resources is a challenging task.

Error Control Coding Algorithms in High Reliability Telemetry Systems

In the oil and gas industry, in the process of drilling support (geosteering) and well telemetry, there is a problem of transmitting reliable information via wireless communication channels. The quality of such communication, as a rule, suffers due to the presence of errors caused by interference. As the depth of the well increases, the problem becomes more extensive. In order to solve the problem, it is proposed to choose noise-resistant coding in the system of residual classes. This system parallelizes the execution of arithmetic operations, has corrective abilities and organically adapts to the neural network basis of intelligent field management. At the same time, there are constraining factors for the mass application of the RNS; for example, difficulties in implementing non-modular procedures, forward and reverse coding, and some difficulties in identifying and correcting errors. That is why the task of improving the RNS seems relevant not only for oil and gas complexes, but also for any digital signal processing applications focused on intelligent neural network management on the basis of non-positional computing. The material of the article is limited to the study of the noise immunity of linear codes of the deduction system and the development of algorithms for detecting and correcting errors.