Abstract
Multipliers are highly on demand as they are used in tremendous areas such as digital signal processing applications, image processing application , and in various Microprocessors such as ARM, NVIDIA, Intel, DSP Processors such as DM270,DM320 etc. Many researchers are urging to improve the performance of the multipliers by adopting various methods. Most of the existing papers includes the work on Array multipliers, Wallace tree multiplier, Dadda multiplier and Booth multipliers. And few recent papers include Vedic Mathematics that have implemented most commonly used Urdhva Sutra. In this paper, various methods are implemented to design a multiplier such as Booth multiplier, Modified Booth multiplier, Urdhva multiplier and Nikhilam multiplier. All the methods are used to design for 8bit signed numbers by coding very efficiently in Verilog. This paper focuses on the design of multipliers that are very simple in structure such that there is no circuit complexity. The design is simulated using Xilinx ISE or ModelSim SE.
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