Digital Front-end Research Articles

A Low Power DVB-T/H Zero-IF Tuner IC Design in 0.25 $\mu{\hbox {m}}$ BiCMOS Technology for Mobile TV Reception

This paper describes fully integrated RF IC sub-system of a DVB-T/H receiver intended for Mobile TV reception. The architecture of the RF IC has been designed to be compliant with the category b2 & c of the MBRAIMoBile Radio Access Interface. specification developed for the introduction of TV into existing mobile phone. The coexistence with GSM transceivers has been taken into account to establish the complete link budget from UHF antenna down to the Digital Front-end. A broadband LNA has been designed for an overall IC noise figure of 3.9 dB. The IIP3 is -5 dBm while 25 dBm RF IIP2 has been measured. A 5th order low pass filter has been implemented for adjacent channel suppression. The total power consumption is 150 mW in continuous mode. Thanks to a new broadband synthesizer architecture using a single VCO, the occupied silicon area is 2.2 mm2 in a 0.25 mum BiCMOS technology

New embedded digital front-end for high resolution PET scanner

This work describes a new digital front-end for a high-resolution low-cost animal PET scanner which is currently under development. The advances in flexibility and size of modern FPGAs together with the release of new tools enable the integration of most of the front-end electronics in a single FPGA. The implemented system includes a small 32-bit RISC processor, several peripherals attached to the internal buses and a special DSP unit closely attached to the processor which is dedicated to the detection of the gamma events. On top of these, a small footprint real time operating system abstracts the underlying hardware, providing the mechanisms to combine on-chip slow control and data streaming.

The BTeV RICH front end electronics

We report on the design and testing of novel mixed analog and digital front end ASICs custom made for the single photon detectors considered for the BTeV RICH system. The key features are reviewed, as well as results achieved using electronics bench tests and beam studies.

A Digital Front-End Supported Frequency Agile Multi-Standard Wireless Receiver

A Digital Front-End Supported Frequency Agile Multi-Standard Wireless Receiver

MAPMTs and FE electronics for the LHCb preshower readout

The LHCb preshower is a scintillator plane preceded by a lead sheet of 2.5 radiation lengths. Its main task is to validate the electromagnetic nature of the showers for the Level 0 trigger. The readout system, working at the LHC frequency, has a large dynamics, high accuracy and allows successive triggers. It includes 64 anode photomultiplier tubes, an analogue very front end board and a digital front end board. The full readout system will be described in the following.

First results of VLSI Front End Electronics for photo detectors

The first prototype for the EUSO Digital Front End Electronics VLSI chip has been developed by the INFN Genova group, and now it is in advanced test and characterization phase. An outline of the entire project is given, focusing the subject on the preliminary results we obtained during bench test in the last months.

Calorimeter prototype based on silicon drift detectors coupled to scintillators for Compton telescopes application

The project of a new calorimeter module for Compton telescopes based on an array of silicon drift detectors (SDD) coupled to thallium activated cesium iodide (CsI(Tl)) scintillating crystals is presented. Because of their low output capacitance and the possibility to have the first amplifying stage directly integrated on chip, SDDs show better noise performances than traditional p-intrinsic-n (PIN) photodiodes. For this reason, SDDs coupled to scintillators show a higher energy resolution than similar systems based on PIN photodiodes. The detectors will be integrated in an array with read-out based on custom made ASIC’s built to match with the SDDs electrical properties. Shaped signals are digitally converted by a Digital Front-End Electronic Board which also takes care of ASICs handshaking. The system architecture is based on the PICsIT instrument on board the INTEGRAL satellite, at present fully operative. In this paper an overview of the instrument will be given and the status of the project will be reported.

Digital front end electronics design for the EUSO photon detector

In this paper we will present the design status of the Digital Front End Electronic system (DFEE), that will be used for the EUSO photon detector. The DFEE is able to count the single photoelectrons coming form the detector for a given time period, store the numbers in a memory buffer and read them out after a trigger, using a serial communication line. Because of space, mass and power consumption constraints, the system will be implemented in an ASIC using a deep submicron technology. The actual design follows the original ideas of the system, though adding several new functionalities. A fully functional prototype chip has been submitted for fabrication in fall 2002. Extensive tests will be performed on it both with bench instrumentations and with the real sensor (the multi anode photomultiplier Hamamatsu R7600-M64), expecting significant results by early Summer 2003. Future work is needed to convert the design into a more robust RAD-hard technology, suitable for space applications and to include in the final die an additional circuit used to optimize the performances at high photons rates: the Analog Front End Electronics (AFEE). Moreover the base board used to house the multi anode photomultipliers is presented: it is the back-bone of the microcell and will be the basic block used to build up the EUSO focal surface.

A Scalable Media Processor Based Image Data Path for the Xerox DocuSP Platform

The Xerox Document Services Platform (DocuSP) is the Xerox Digital Front End platform for production products. DocuSP supports over 26 different production engines that include monochrome, color, cut sheet, and continuous feed products. In particular DocuSP is one of the Digital Front Ends for the Xerox iGen3 Digital Press. This talk will describe some unique technologies in the DocuSP DFE that enable high performance printing at 100 pages per minute in full color. Unique to this controller is the concept of a scalable performance, “soft” image data path, implemented in array of low cost media processors from Equator Technologies that provide the image processing required for full performance printing on iGen3. This allows DocuSP to be an agile platform to support new imaging features without the overhead of lengthy hardware development.

A self-calibrated pipeline ADC with 200MHz IF-sampling frontend

A 13b 50MSample/s pipeline ADC with digital self-calibration and IF-sampling frontend, using a 0.35/spl mu/m BiCMOS process, achieves 76.5dB SFDR at 194MHz input. The chip occupies 6mm/sup 2/ and dissipates 715mW from a 2.9V supply.

The space-borne INTEGRAL-SPI gamma ray telescope: test and calibration campaigns

The spectrometer SPI aboard the ESA INTEGRAL satellite, which will be launched in 2002, will study the gamma ray sky in the 20-keV to 8-MeV energy band. It achieves the excellent spectral resolution of about 2 keV for photons of 1 MeV thanks to its 19 germanium detectors. A coded mask imaging technique provides an angular resolution of 2/spl deg/. An active BGO veto shield is used for the definition of the field of view and for background rejection. After integration and testing at CNES in Toulouse, the flight model of SPI recently underwent a one-month prelaunch calibration at the CEA center of Bruyeres le Chatel, using an accelerator for homogeneity measurements and high-activity radioactive sources for imaging performance measurements. This paper presents the scientific goals and the different detector components of SPI and reports on the testing and calibration campaigns. The methods used to achieve good timing alignment using the digital front end electronics are described and the first detector performance and imaging capabilities are presented.

PICsIT: a position sensitive detector for space applications

Pixellated Imaging CsI Telescope (PICsIT) is the high energy detector plane of Imager on Board INTEGRAL Satellite (IBIS), one of the main instruments on board the International Gamma-Ray Astrophysics Laboratory (INTEGRAL) satellite that will be launched in the year 2001. It consists of 4096 CsI(Tl) individual detector elements and operates in the energy range from 120 to 10,000 keV. PICsIT is made up of 8 identical modules, each housing 512 scintillating crystals coupled to PIN photodiodes (PD). Each crystal, 30 mm long and with a cross-section of 8.55×8.55 mm 2, is wrapped with a white diffusing coating and then inserted into an aluminium crate. In order to have a compact design, two electronic boards, mounted directly below the crystal/PD assembly, host both the Analogue and Digital Front-End Electronics (FEE). The behaviour of the read-out FEE has a direct impact on the performance of the whole detector in terms of lower energy threshold, energy resolution and event time tagging. Due to the great number of channels to be handled, an Application Specific Integrated Circuit (ASIC), that manages signals coming from groups of 16 detecting units, has been designed. The first reduced model of a PICsIT module has been now constructed and is under intensive tests in order to evaluate the main qualification parameters of the detector. In this paper, after a description of the PICsIT hardware and assembly procedures, the main results on system functionality are presented.

Repurposing Device-dependent Screens for Unintended Printers

Screened images of 1-bit depth are common in the office market and in graphic-arts printing systems. Bitmapped screens are produced at the copier scanner, copy-dot scanners and in the Digital Front End (DFE) as “digital negatives.” Raster-once-output-many (ROOM) is an example of a digital negative. Such bilevel images are printer device specific. The bilevel image may be inappropriate for the printer in use and the original image may be unavailable.While inverse halftone is a common solution for repurposing screened images, it results in lower quality reproduction:• Inverse halftoning requires further density compensation for the requirements of the new printer.• Much of the original image information is lost in the depth to frequency conversion and inverse halftoning cannot reclaim the lost image data.• Rescreening a reverse-halftone image results in loss of high-spatial frequency image data.The goal of the algorithm described is to increase screen-repurposing performance and maintain high-frequency detail without inverting the 1-bit image to 8-bit.

Multi Mission Data Simulator for Checking Ground Segment Elements of Indian Remote Sensing (IRS) Satellite Ground Stations

This paper describes the design and development of Multi Mission Data Simulator at National Remote Sensing Agency (NRSA), which is used for checking various Ground Segment Elements like Down Converter, Demodulator, Bit Synchroniser, High Density Digital Tape Recorder (HDTR) and Front End Hardware of Indian Remote Sensing Satellite (IRS) Ground Stations, during prelaunch and normal phase of satellite acquisition operations and Data Products (Imageries) generation.

Fast detector readout for the HADES-RICH

The readout electronics for the HADES RICH uses new concepts for the data transport and a multilevel trigger scheme for online data reduction. We have developed two types of modules for the readout of the RICH detector that is used for lepton identification in the HADES spectrometer. The first one is a mixed analog and digital frontend module that converts the charge signals from the detector to digital data words. The second module controls the digital readout of the frontend modules and the transport of the event data to a VMEbus memory.

The digital front-end of software radio terminals

When expanding digital signal processing of mobile communications terminals toward the antenna while making the terminal more wideband in order to be able to cope with different mobile communications standards in a software radio based terminal, the designer is faced with strong requirements such as bandwidth and dynamic range. Many publications claim that only reconfigurable hardware such as FPGAs can simultaneously cope with such diversity and requirements. Starting with considerations of the receiver architecture, we describe key functionalities of the digital front-end and highlight how the signal characteristics of mobile communications signals and commonalities among different signal processing operations can be exploited to great advantage, eventually enabling implementations on an ASIC that, although not reconfigurable, would empower the software radio concept.

The digital ASIC for the Digital Front End Electronics of the SPI astrophysics gamma-ray experiment

The SPI spectrometer is one of the gamma-ray astronomy instruments that will be installed on the ESA INTEGRAL satellite intended to be launched in 2001 by the European Space Agency. The Digital Front-End Electronics sub-system (DFEE) is in charge of the real time data processing of the various measurements produced by the germanium (Ge) detectors and the Bismuth Germanate (BGO) anti-coincidence shield. The central processing unit of the DFEE is implemented in a digital ASIC circuit, which provides the real time association of the various time signals, acquires the associated energy measurements, and classifies the various types of physics events. The paper gives the system constraints of the DFEE, the architecture of the ASIC circuit, the technology requirements, and the strategy for test and integration. Emphasis is given to the high level language development and simulation, the automatic circuit synthesis approach, and the performance estimation.

MEC3-a pipelined zero suppression and trigger matching chip

The MEC3 chip is a demonstrator of the general purpose MEC architecture. This architecture is intended for the digital front-end of detector channels where the detector signal is sampled at constant rate. In addition to simple storage during the first level trigger latency, data of interest are extracted by zero suppression and trigger matching. An event synchronized read-out interface takes care of merging event data from several channels. The three main ports (1: sampled data in, 2: trigger and 3: read-out), can run completely asynchronously. The synchronization of the three ports inside the chip is performed at the event level by the use of time tags and FIFOs. Zero suppression is performed by adaptive thresholding that takes baseline variations into account. In addition a programmable FIR filter is available to process the signal before the pulse detection thresholding. Trigger matching is done by a comparison between time tags of the extracted pulses and the trigger decision. All functions are implemented with a high level of programmability to accommodate different signal characteristics. Also special handling of channel pile-up and clustering has been included. Extensive simulations at behavioral level have been performed to optimize the architecture and an ASIC has finally been implemented with standard cells in a 1.0 /spl mu/m CMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parallel and pipelined front-end for multi-element silicon detectors in scanning electron microscopy

A silicon quadrant detector (128 elements) was implemented as an electron detector in a scanning transmission electron microscope. As the electron beam scans over the sample, electrons are counted during each pixel. An ASIC was developed for the multichannel counting system. The digital front-end carries out the readout of all elements, in four groups, and uses these data to computer linear combinations to generate up to eight simultaneous images. For the preprocessing a parallel and pipelined system was implemented. Dedicated software tools were developed to generate the programs for all the processors. These tools are transparently accessed by the user via a user-friendly interface.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>