MEC3-a pipelined zero suppression and trigger matching chip

Abstract

The MEC3 chip is a demonstrator of the general purpose MEC architecture. This architecture is intended for the digital front-end of detector channels where the detector signal is sampled at constant rate. In addition to simple storage during the first level trigger latency, data of interest are extracted by zero suppression and trigger matching. An event synchronized read-out interface takes care of merging event data from several channels. The three main ports (1: sampled data in, 2: trigger and 3: read-out), can run completely asynchronously. The synchronization of the three ports inside the chip is performed at the event level by the use of time tags and FIFOs. Zero suppression is performed by adaptive thresholding that takes baseline variations into account. In addition a programmable FIR filter is available to process the signal before the pulse detection thresholding. Trigger matching is done by a comparison between time tags of the extracted pulses and the trigger decision. All functions are implemented with a high level of programmability to accommodate different signal characteristics. Also special handling of channel pile-up and clustering has been included. Extensive simulations at behavioral level have been performed to optimize the architecture and an ASIC has finally been implemented with standard cells in a 1.0 /spl mu/m CMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>