A closed-loop ASIC design approach based on logical effort theory and artificial neural networks

Abstract

Standard cell library is the backbone of modern day application specific integrated circuit (ASIC) design flow provided by electronic design automation (EDA) vendors worldwide. In these libraries, standard cells are generally available in terms of discrete drive strengths with higher drive strength indicating a faster version of the cell belonging to some predefined logic functionality. However, this leads to increased values of area and power consumption in comparison to a lower drive strength standard cell which has slower response time indicating the underlying tradeoff between speed, area and power. A standard cell with discrete drive strength is not always required during the process of logic synthesis and non-availability of standard cells with fractional drive strengths in the aforementioned libraries hugely impacts the overall performance of resulting digital integrated circuits (ICs) and systems [1]. In this paper, a novel technique has been introduced for on-demand generation and inclusion of standard cells in the logic synthesis process leading to availability of a continuous spectrum of standard cells in terms of drive strengths which ultimately provides a platform for closed-loop ASIC design flow. Logical effort (LE) theory has been utilized alongside artificial neural networks (ANNs) in order to implement the proposed methodology. Extensive circuit simulations have been performed using HSPICE in 130 nm/1.2 V CMOS process technology. Preliminary results are encouraging with up to 41.7% and 62.8% reduction in power-delay product (PDP) and power-delay-area product (PDAP) for a 5-stage gate level test circuit. An 8-bit counter realized using the proposed methodology shows up to 29.77% reduction in power dissipation and 37.8% savings in area at varying capacitive loads when compared to conventional logic synthesis technique which employs a library comprising of standard cells with discrete drive strengths. It is noteworthy that the proposed approach is a general technique which can be easily mapped to high complexity circuits and advanced technology nodes. To support this fact, simulation results have also been provided at 90 nm/1 V CMOS process node for the 5-stage test circuit.