Digital Front-end Research Articles

A low-complexity crest factor reduction design for 5G NR sub-6 GHz digital front-end with restricted peak regrowth

In recent years, orthogonal frequency division multiplexing (OFDM) has gained widespread adoption in communication technologies, exemplified by long-term evolution (LTE), 5th generation new radio (5G NR sub-6 GHz), and others. These technologies are instrumental in meeting the increasing demands for high data rates, throughput, and reliable downlink network access. However, a notable challenge associated with OFDM is the high peak-to-average power ratio (PAPR), imposing limitations on the efficiency of power amplifiers that often operate with significant back-offs. To mitigate this issue, the widely employed crest factor reduction (CFR) technique aims to enhance efficiency. This paper introduces a novel CFR methodology utilizing mixed and multi-iterative signal distortion-based techniques. Our approach is versatile, demonstrating effectiveness for low-bandwidth signals like LTE, as well as large-bandwidth signals reaching up to 100 MHz, as seen in 5G NR FR1. Also, digital up-sampling used to achieve the required high sample rate causes the issue of peak regrowth even after the required PAPR reduction achieved by CFR processing, which defeats the purpose of CFR. Our proposed design offers a solution to this challenge, enabling operation at a low data rate before digital up-sampling while effectively mitigating peak regrowth. Importantly, the implementation significantly reduces FPGA resource utilization, alleviating the complexity associated with multiple-input multiple-output (MIMO) radio systems. Demonstrating compliance with 3rd generation partnership project (3GPP) specifications for 5G NR on a real-time testbed, our approach stands as a practical and efficient solution for contemporary communication systems.

A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios

We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-power microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are often energy-constrained, the underlying challenge is to implement the digital signal processing of the radio in software while maintaining an overall very low power consumption. To overcome this problem, we propose an ultra low-power microcontroller architecture with an ARM Cortex-M4 processor for the protocol-specific computations and a hardware digital front-end for the generic signal processing. The proposed architecture has been prototyped in 28nm FDSOI and the physical layers of the well-known LoRa and Sigfox protocols have been implemented in software. Thanks to the efficient hardware/software partitioning and an ultra-low power digital implementation, experimental evaluations of the microcontroller prototype show sub-mW power consumptions (32 – 332 μW) for the digital signal processing of the software-defined radios.

Performance and Integration Results of a High Resolution Time-to-Digital Converter Designed for INO ICAL Experiment

INO ICAL Experiment emphasis on studying various properties of atmospheric neutrinos. A 50 kton Iron Calorimeter and Resistive plate Chamber (RPC) in stacked geometry will be used to track neutrinos. Position and directional information are to be used to identify particle energies. RPC detector signal of rise time less than 1ns is amplified-discriminated and given to Digital Front End (RPC-DAQ). To measure these fast pulses, we designed a low power, compact multi-channel Delay Chain based time-to-digital converter (TDC) in a 0.13μm CMOS process which will be integrated with the RPC-DAQ module. This TDC is capable of handling multiple hits per channel with a single-shot precision better than 65.34 ps. A 4-line or 11-line serial peripheral interface (SPI) is used for readout and configuration. This paper presents the performance and integration results of this TDC.

Charge Collection Dynamics of the ARCADIA Passive Pixel Arrays: Laser Characterization and TCAD Modeling

Monolithic Active Pixel Sensors (MAPS) represent one of the most promising technologies for the next generation of radiation detectors. The ARCADIA project aims at the development of Fully Depleted (FD) MAPS employing a production process compatible with a 110 nm commercial CMOS technology. The first engineering run of the project included matrices of active pixels with embedded analog and digital frontend electronics and passive test structures such as passive pixel arrays, MOS capacitors and backside diodes. Although the produced samples were already characterized from the electrical point of view, a thorough study of the charge collection dynamics of the passive pixel arrays was still missing. In this paper we show the results of the dynamic characterization of a group of passive pixel arrays with different pixel pitches (50, 25 and 10 μm) and different pixel layouts. The tested samples have been illuminated from the backside with an infrared and a red laser with wavelengths equal to 1,060 nm and 660 nm, respectively. The pixel arrays have been mounted on a custom readout PCB connected to an external amplifier with 1 GHz bandwidth and the signals have been acquired through a fast digital oscilloscope. We employed both focused and unfocused laser spots to evaluate the change in the measured signal as a function of the laser spot position and the average response of the pixel arrays. An excellent agreement has been demonstrated by comparing the measured signals with the results of transient TCAD simulations and a time for 50% charge collection of 7.8, 4.2 and 2.6 ns has been predicted and experimentally validated in pixels with 50, 25 and 10 μm pitch, respectively.

Development of a single-photon imaging detector with pixelated anode and integrated digital read-out

We present the development of a single-photon detector and the connected read-out electronics. This “hybrid” detector is based on a vacuum tube, transmission photocathode, microchannel plate and a pixelated CMOS read-out anode encapsulating the analog and digital-front end electronics. This assembly will be capable of detecting up to 109 photons per second with simultaneous measurement of position and time.The pixelated read-out anode used is based on the Timepix4 ASIC (65 nm CMOS technology) designed in the framework of the Medipix4 collaboration. This ASIC is an array of 512 × 448 pixels distributed on a 55 μm square pitch, with a sensitive area of ∼7 cm2. It features 50–70 e− equivalent noise charge, a maximum rate of 2.5 Ghits/s, and allows to time-stamp the leading-edge time and to measure the Time-over-Threshold (ToT) for each pixel. The pixel-cluster position combined with its ToT information will allow to reach 5–10 μm position resolution. This information can also be used to correct for the leading-edge time-walk achieving a timing resolution of the order of 10 ps.The detector will be highly compact thanks to the encapsulated front-end electronics allowing local data processing and digitization. An FPGA-based data acquisition board, placed far from the detector, will receive the detector hits using 16 electro-optical links operated at 10.24 Gbps. The data acquisition board will decode the information and store the relevant data in a server for offline analysis.These performance will allow significant advances in particle physics, life sciences, quantum optics or other emerging fields where the detection of single photons with excellent timing and position resolutions are simultaneously required.

A Systematic Solution for the Problem of Spectral Degradation in Multiphase TX Architectures

With ever more stringent requirements of cellular standards it is an ongoing challenge to find the optimal RF transmitter architecture. In recent years, the multiphase transmitter (MP TX) architecture has been introduced as a promising candidate. It features high power efficiency and avoids phase modulation which is critical for upconversion of ultra-wideband signals. In this brief, the problem of unwanted spectral emission, inherent in MP TX architectures, is compensated by a proper data delay. Such an approach is considered for the first time in the multiphase architecture and achieves a spectral improvement of up to 38 dB in adjacent channels and 24 dB at the receiver (RX) duplex distance for a new radio (NR) signal with 20 MHz bandwidth. With the proposed solution the MP TX architecture becomes a highly competitive candidate for wideband signals such as LTE, LTE-CA or NR signals. In addition, a detailed and efficient implementation of the digital front-end (DFE) for the MP TX architecture including the proposed data delay is presented.

Integrated Remote Laser Source for 6G Advanced Antenna Systems

Future generations of mobile communications promise near unlimited access to information and data sharing with ubiquitous wireless connectivity for any kind of device and application that may benefit from being connected. This poses new design challenges and requires a renewal of the hardware platforms to meet the increased demand of capacity and reliability of the network. Next generation Radio Access Network (RAN) will evolve towards an increase of the radio bandwidth, with carrier frequency extended to the millimeter waves (mmW) range. Other technologies that will be extensively used to increase the RAN capacity will be beamforming and spatial multiplexing with advanced antenna systems (AAS) comprising hundreds of antenna elements. Optical technologies are the natural candidates to support the traffic increase, by providing high-capacity interconnection within the radio unit and towards the base band unit (BBU). However, the higher level of integration of AAS will cause an increase of the temperature to values >100C, due to power dissipation of RF power amplifiers (PA), digital front-end (DFE) and baseband processing Application Specific Circuits (ASIC). This makes the AAS an inhospitable environment for optical transceivers that include lasers, typically operating at temperatures <85C. A promising approach to solve this issue is to place the laser outside the transceiver as a remote laser source (RLS) in a less harsh environment or in a thermally controlled environment e.g. in the same cabinet of the BBU. In this article we demonstrate a fully integrated RLS enabling a reduction of power consumption and packaging cost.

An IR-UWB IEEE 802.15.4z Compatible Coherent Asynchronous Polar Transmitter in 28-nm CMOS

A low-power IEEE 802.15.4z high-rate PHY (HRP) compatible coherent transmitter is described. The proposed transmitter uses a digital polar architecture with fixed amplitude steps in the power amplifier and asynchronous time-discrete pulse shaping. The pulse-shaping unit consists of a finite-impulse response (FIR) filter using current-starved inverter-based delay taps that can be calibrated on-chip. An injection-locked ring oscillator (ILRO)-based frequency synthesis enables wideband operation from 3- to 10-GHz frequency bands. The ILRO also allows for duty-cycled coherent mode operation with 2–4-ns phase locking time and binary phase modulation is applied directly on the oscillator. The on-chip digital front end enables duty cycling (DC) of analog front-end modules with a granularity of 2 ns. Implemented in 28-nm CMOS process, this chip is measured to consume 4.9-mW power in nominal mode with IEEE 802.15.4z high pulse repetition frequency (HPRF) compatible data rate of 6.81 Mb/s compliant with major spectrum mask regulations for channels 5 and 9. With DC of the oscillator enabled in the energy-efficient mode, a power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$430~\mu \text{W}$ </tex-math></inline-formula> is achieved for packets compatible with legacy pulse-position-modulated IEEE 802.15.4a standard with a data rate of 27.2 Mb/s.

Smart Portable Pen for Continuous Monitoring of Anaesthetics in Human Serum With Machine Learning

Continuous monitoring of anaesthetics infusion is demanded by anaesthesiologists to help in defining personalized dose, hence reducing risks and side effects. We propose the first piece of technology tailored explicitly to close the loop between anaesthesiologist and patient with continuous drug monitoring. Direct detection of drugs is achieved with electrochemical techniques, and several options are present in literature to measure propofol (widely used anaesthetics). Still, the sensors proposed do not enable in-situ detection, they do not provide this information continuously, and they are based on bulky and costly lab equipment. In this paper, we present a novel smart pen-shaped electronic system for continuous monitoring of propofol in human serum. The system consists of a needle-shaped sensor, a quasi digital front-end, a smart machine learning data processing, in a single wireless battery-operated embedded device featuring Bluetooth Low Energy (BLE) communication. The system has been tested and characterized in real, undiluted human serum, at 37C. The device features a limit of detection of 3.8M, meeting the requirement of the target application, with an electronics system 59% smaller and 81% less power consuming w.r.t. the state-of-the-art, using a smart machine learning classification for data processing, which guarantees up to twenty continuous measure.

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

Design and Implementation of a Digital Front-End With Digital Compensation for Low-Complexity 4G Radio Transceivers

A digital front-end with digital compensation is designed and implemented for low-complexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a >40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.

Security Transmission in MIMO Ubiquitous Power Internet of Things Systems

Power line communication (PLC) is a promising technique because of its wide distribution and low cost. However, due to the feature of PLC channel, the communication quality is unsatisfactory and there exists security risks. In this paper, we design a frequency division (FD) multiple-input and multiple-output (MIMO) PLC system. Firstly, since power line channels have frequency selectivity problems, it is necessary to select an appropriate frequency band for communication, so we adopt digital front-end (DFE) in the PLC system. The DFE is used to adjust the frequency and bandwidth configuration of the carrier signal. In order to determine the optimal frequency point for upstream and downstream communication, a sweep mechanism under the FD PLC system is designed. The analysis of the sweeping mechanism finds that the sweeping overhead only requires 2N +1 communications, which greatly improves the sweeping efficiency. Secondly, we find this frequency division technology can also be used to enhance the security of MIMO PLC. The real signal can be hidden in the frequency domain and obfuscated in the time domain by using DFEs to adjust the frequency and bandwidth information of the real signal and artificial interference noise. Simulation indicates that the proposed method can guarantee the correct reception and demodulation at the legitimate receiving user end, while the BER at the eavesdropping user end fluctuates around 0.5, thus cannot correctly demodulate the real signal.

Characteristics of High Performance Value Streams

Mass customisation aims at supplying individualised products to a wide customer base, while achieving costs comparable to mass production. However, the degree of individualisation of mass customised products is limited. Certain companies achieve to combine the high product individuality provided by the engineer-to-order concept with the efficiency of mass customisation. By using web-based technologies, these companies integrate the customer into their order processing. Through a digital frontend, the customer is enabled to configure, lay out or design the desired individual product within a defined product solution space. In combination with an automated production preparation and a production process capable for the entire solution space, these companies produce individual products within shortest lead times at low costs. Due to the combination of high product individuality at extremely short lead times as well as competitive costs, the authors name this concept High Performance Value Stream.This paper characterises the concept of High Performance Value Streams and points out the main aspects. In a series of interviews, High Performance Value Streams within the industry were analysed. Characteristic types as well as examples from the industry are pointed out. For relevant aspects of the order fulfilment process of individual and individualised products, morphological boxes with distinctive features are presented.

Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process

Tunnel FET is recognized as one of the most promising candidates for ultra-low power applications due to its ultra-low off current and CMOS compatibility. However, some characteristics of TFET caused by asymmetric device structure and special conduction mechanism may make conventional topologies of logic circuits no longer applicable. Our previous work has reported that TFET stacking will result in severe current degradation, which makes traditional logic cells not applicable. In this paper, two solutions are proposed: first, from a logic cell perspective, novel hybrid TFET-MOSFET topologies of standard logic cells are proposed, which achieve more than 2 times lower hardware cost and intrinsic delay, hence up to 4 times lower area-power-delay product (APDP) than that of conventional TFET logic circuits. Compared to MOSFET logic circuits, the designs achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP. Second, from a large-scale circuit perspective, an optimized digital front-end (DFE) is proposed. Taking serial peripheral interface (SPI) as an example, SPI circuit using the optimized DFE achieves 46% lower delay and 4 times lower APDP than that of traditional TFET SPI, and 3 orders of magnitude lower static power and APDP than that of MOSFET SPI.

Passive Intermodulation in Simultaneous Transmit–Receive Systems: Modeling and Digital Cancellation Methods

This article presents novel solutions for suppressing passive intermodulation (PIM) distortion in frequency-division duplexing (FDD)-based radio transceivers, stemming from nonlinear radio frequency (RF) components and simultaneous transmission and reception, with special emphasis on modern carrier aggregation networks. With certain transmission band combinations in, e.g., long-term evolution (LTE) or the emerging 5G new radio (NR) mobile radio systems, the nonlinear distortion produced by the passive components of the transceiver RF front end can result in intermodulation (IM) distortion that falls within one of the configured reception bands. While the traditional solution to mitigate this problem is to reduce the transmit power, we take an alternative approach and seek to cancel such PIM in the transceiver digital front end by using the original transmit data as a reference. To generate as accurate cancellation signal as possible, we derive different advanced signal models for the observable IM distortion at own receiver band that incorporates also the power amplifier (PA) nonlinearities, together with the passive component nonlinearities and the frequency-selective responses of the duplex filters. The performance and the processing complexity of the devised digital cancellation and parameter estimation solutions are evaluated with real-life RF measurements, where an actual LTE-Advanced user equipment (UE)-type transceiver system is utilized. The obtained results show that the proposed cancellers are implementation feasible and can suppress the self-interference by over 20 dB, canceling the distortion nearly perfectly up to UE transmit powers of +24 dBm. The results also indicate that, in many cases, it is necessary to model the nonlinear distortion effects produced by the PAs, even if the individual component carriers are combined after the amplification stage.

Initial Access through Beamforming in mmWave

Future Wi-Fi, 5G Cellular and millimetre-wave (mmWave) will depend on highly directional links in order to prevail over exuberant path loss experienced in the different bands of frequency. However, in order to establish these type of links, the receiver and transmitter need mutual discovery which will result in high energy consumption and large latency. The proposed work deals with reduction of energy consumption and latency significantly with the help of a fully digital front-end. The digital beamformer will receive the spatial samples within a shot, from all directions. However, in analog front-ends, sampling is allowed for beamforming in one particular direction at a time resulting in the time period in which the mobile is “on” for longer. This will result in an increase in energy consumption by more than four times for the analog front-end when compared with digital front-ends, taking into consideration the antenna arrays’ size. However, from the power consumption point of view, using a fully digital beamforming post beam discovery is not recommended. Hence in order to overcome this drawback, a digital beamformer coupled with a 4-bit A-D convertor with low resolution is proposed. The use of low resolution will decrease the power consumption such that it is in the same zone as that of analog beam forming while it is possible to make use of the fully digital beamforming spatial multiplexing capabilities resulting in improved energy efficiency and reduced discovery latency.

Energy Efficiency of Multiple-Input, Multiple-Output Architectures: Future 60-GHz Applications

Large antenna systems at millimeter-wave (mmwave) can concentrate the transmit power and the receive region over narrow beams, as well as enable spatial multiplexing. Thanks to these benefits, large antenna systems at mm-wave are the core technologies for future wireless local area network (WLAN) and 5G/ beyond 5G (B5G) cellular standards. Energy efficiency is a crucial design objective for new technologies to reduce operating costs, minimize the environmental impact, and enable battery-powered applications. Power consumption and system performance depend on the design of the beamforming architecture. The objective of this article is to compare the energy efficiency of three different architectures using power consumption measurements of a 60-GHz CMOS transceiver. We compare a full digital architecture, in which each digital chain is connected to a single antenna, against hybrid partially connected (HPC) and hybrid fully connected (HFC) architectures, using fewer digital chains than antennas. The system throughput performance is evaluated considering the hardware nonidealities, including power amplifier saturation, quantization, and phase noise (PN). We show that the number of users spatially multiplexed impacts the hybrid beamforming tradeoff. When few users are multiplexed, the main drain of energy is the digital front end, as it needs to execute operations such as filtering and fast Fourier transform (FFT) on a wide modulation bandwidth of 1.76 GHz. In this case, reducing digital redundancy using a hybrid architecture is beneficial, and a HPC architecture is the most attractive. Scaling the system to a massive multiple-input, multiple-output (mMIMO) scenario instead allows full digital architectures to achieve the highest energy efficiency.

Double-Sequence Frequency Synchronization for Wideband Millimeter-Wave Systems With Few-Bit ADCs

In this paper, we propose and evaluate a novel double-sequence low-resolution frequency synchronization method in millimeter-wave (mmWave) systems. In our system model, the base station uses analog beams to send the synchronization signal with infinite-resolution digital-to-analog converters. The user equipment employs a fully digital front end to detect the synchronization signal with low-resolution analog-to-digital converters (ADCs). The key ingredient of the proposed method is the custom designed synchronization sequence pairs, from which there exists an invertible function (a ratio metric) of the carrier frequency offset (CFO) to be estimated. We use numerical examples to show that the ratio metric is robust to the quantization distortion. To implement our proposed method in practice, we propose to optimize the double-sequence design parameters such that: (i) for each individual user, the impact of the quantization distortion on the CFO estimation accuracy is minimized, and (ii) the resulting frequency range of estimation can capture as many users' CFOs as possible. Numerical results reveal that our proposed algorithm can provide a flexible means to estimate CFO in a variety of low-resolution settings.

Digital frontend design for three-bands aliasing RF signals

Digital frontend design for three-bands aliasing RF signals

A novel hybrid narrowband/wideband networking waveform physical layer for multiuser multiband transmission and reception in software defined radio

Increasing demands of adaptability and reconfigurability impose many challenges on the design of Software Defined Radio (SDR) waveforms for highly heterogeneous wireless networks. Usually, narrowband waveforms provide robustness and work for longer distances but lack in providing higher throughput, whereas wideband waveforms provide much higher throughput but they are not much robust and operate for smaller distances. A heterogeneous SDR network having diverse Quality of Service (QoS) and range requirements, and channel conditions cannot fully rely on one of the narrowband or wideband waveform. In this paper, a novel hybrid narrowband/wideband networking waveform physical layer is proposed. The proposed waveform is based on simultaneous transmission and reception of signals having multiple bandwidths through minimal changes in the existing analog wideband front end. A digital front end architecture is proposed where sample rate conversion and channelization of multiple signals at the digital front end formulate a composite signal which is then transmitted by using the wideband RF front end settings of a wideband waveform. At the receiver, the composite signal is received by using the wideband RF front end configured to wideband mode. Individual downconversion and filtering of each of the respective signal is done digitally. In this way, multiple signals having bandwidths as per their QoS and range requirements can be transmitted/received through the same wideband front end. As a proof of concept, the proposed idea is validated on actual SDR platform by taking actual dumps from FPGA and DSP. The presented results show the viability of the proposed hybrid SDR waveform.