Abstract
A digital front-end with digital compensation is designed and implemented for low-complexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a >40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.
Highlights
Modern radio transceiver chips tailored to various wireless standards such as WLAN and LTE often include digital circuits immediately after the analog-to-digital converter (ADC) in the receiver and immediately before the digital-toanalog converter (DAC) in the transmitter
Placing the digital compensation circuits inside the radio transceiver chip is helpful in readily fixing radio frequency (RF) analog impairments which are inherent in the same radio chip
We formerly modeled, designed, and implemented a DFE Rx with fractional sample rate conversion in an ASIC [3]
Summary
Modern radio transceiver chips tailored to various wireless standards such as WLAN and LTE often include digital circuits immediately after the analog-to-digital converter (ADC) in the receiver and immediately before the digital-toanalog converter (DAC) in the transmitter. A host of literatures address the DFE Rx, the digital compensation circuitry, and the DFE Tx. An analog-digital baseband signal chain is proposed in [6] as a softwaredefined radio receiver to realize flexible multimode operations. In [4], a decimation chain and digital filters are designed for software radio receivers by using fractional sample rate conversion. All the digital compensation circuits are newly designed in this work and included in the proposed DFE Rx. Especially, the DFE Rx with digital compensation includes an anti-drooping filter, a DC offset cancellation (DCOC) circuit which features the adoption of both the infinite-duration impulse response (IIR) filter and the moving average (MA), and a new compact IQ estimation and compensation circuit which uses a coordinate rotation digital computer (CORDIC).
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