Digital Current Mode Control Research Articles

Digital Current-Mode Controller Using Delta Operator and Advance Sampling Predictive Control for High-Frequency DC–DC Switching Converters

High-frequency digitally controlled dc–dc switching converters have many advantages, such as very fast transient response and high-power density. However, the studies of control strategies and algorithms specifically for high-frequency digitally controlled dc–dc converters are seldom reported. In this study, we propose a novel digital current-mode controller consisting of both output voltage and inductor current compensators for high-frequency dc–dc switching converters. The voltage compensator is designed based on the delta operator instead of the shift operator, which could improve the control accuracy and reduce hardware costs. Furthermore, the current compensator is designed using an advanced sampling predictive (ASP) control strategy to reduce the requirement of hardware processing speed, and in turn the hardware cost, and to eliminate the influences of noise caused by power switch commutations. Finally, a buck dc–dc switching converter with a switching frequency of 2 MHz is designed and implemented using the proposed digital current-mode controller on a field-programmable gate array (FPGA) platform. Our test results indicate that better control accuracy and lower hardware costs can be realized using the delta operator instead of using the shift operator. In addition, compared with the single digital voltage compensator, the proposed digital current-mode controller has better transient response performances. The control strategy and algorithm proposed in this study are especially effective for digitally controlled high-frequency dc–dc switching converters.

Discrete-Time Framework for Analysis and Design of Digitally Current-Mode-Controlled Intermediate Bus Architectures for Fast Transient and Stability

In an intermediate bus architecture (IBA), a buck converter, while driving a constant power load (CPL), exhibits unstable poles in its control-to-output transfer function. This may result in limit-cycle oscillations due to the lack of sufficient damping, and an active damping using current-mode control (CMC) can stabilize the converter. However, existing small-signal stability results are not sufficient to ensure the fast-scale stability of the overall IBA system under digital CMC. This article proposes a discrete-time framework to derive necessary and sufficient stability conditions to meet both small-signal and fast-scale stability requirements of a mixed-signal CMC (MCMC) buck converter driving a CPL. The latter is a point-of-load (PoL) converter driven by MCMC with the switching frequency much faster than that of the former. Design methods are proposed for an enhanced stability boundary followed by a nonlinear controller-tuning method for near-time optimal transient recoveries for both the converters by considering a time-scale separation. A buck converter-based IBA prototype is developed, and analytical predictions are verified using the experimental results.

Constant off-Time Digital Current-Mode Controlled Boost Converters With Enhanced Stability Boundary

The right-half-plane (RHP) zero in a continuous conduction mode boost converter results in a significantly restricted closed-loop bandwidth (BW) for higher voltage gain and/or load current conditions. A compensating ramp is used for current-mode control (CMC), and a higher ramp slope degrades the BW. Variable-frequency digital CMC offers inherent current-loop stability and real-time tuning scope for higher closed-loop BW. However, the challenges are to select the sampling frequency and sampling instant of the output voltage with discontinuous ripple due to the effective series resistance of the output capacitor, and its impact on stability. This paper shows that an event-based current-mode constant off -time digital modulator achieves superior stability and performance in a boost converter along with the reduced RHP zero effect over other digital CMC techniques. Using a discrete-time framework, the fast-scale stability conditions and small-signal models are analytically derived for various digital CMC techniques, which are validated using SIMPLIS simulation. A boost converter prototype is tested, and the analytical predictions are verified experimentally. Further, the analysis is extended to a non-inverting buck–boost converter.

Enhanced Stability Caused by a One-Cycle Delay in a Digital Current-Mode Controlled Buck Converter

In the recent years, digital current mode control has gained popularity due to its technical benefits. However, designers face difficulties in controller design due to the delays associated with analog-to-digital (A/D) converter and controller computation. In software-based digital controller implementation, the cumulative delay of A/D conversion and controller computation may be comparable to the switching time period. This brief shows that the one-cycle delay in digital implementation in fact enhances the stability margin in a mixed-signal current mode controlled buck converter. By deriving a discrete-time model, we obtain the stability region in the parameter space and show that, if the controller gain is set within a specific range, the software-based implementation can achieve stable periodic (period-1) behavior without a ramp compensation even when the duty ratio exceeds 0.5. The theoretical results are validated with a buck converter prototype with a digital controller realized on an FPGA device.

Analysing the effects due to discontinuous output‐voltage ripple in a digitally current‐mode controlled boost converter

Digital implementation of current-mode control (CMC) considers the outer voltage-loop in the digital domain, whereas the inner current-loop is kept either in the analogue domain in mixed-signal CMC (MCMC) or in the digital domain in fully digital CMC (DCMC). Under finite voltage-loop sampling, this study reports that the selection of sampling point can completely change the stability status of a boost converter with non-minimum phase behaviour, particularly in the presence of the effective-series-resistance of the output capacitor. A discrete-time framework is proposed for fast-scale stability analysis in a boost converter, operating under continuous conduction mode. Further, discrete-time small-signal models are derived and design guidelines are proposed for both MCMC and DCMC architectures with enhanced stability for fast transient performance. Keeping in mind software-controlled DCMC, a considerably large sampling delay is considered, and its effect on the performance and stability is discussed. A boost converter prototype is tested and various DCMC schemes along the proposed design techniques are implemented using a field-programmable-gate-array device.

A Dual-Mode Driver IC With Monolithic Negative Drive-Voltage Capability and Digital Current-Mode Controller for Depletion-Mode GaN HEMT

This work presents a driver and controller integrated circuit (IC) for depletion-mode gallium nitride (GaN) high-electron-mobility transistors (HEMTs). The dual-mode driver can be configured for cascode-drive (CD) or HEMT-drive (HD) mode. In the CD mode, a cascode low-voltage DMOS is driven to achieve high-speed normally OFF operation. An active clamping circuit is proposed for the DMOS breakdown protection. In the HD mode, an HEMT gate driver with negative drive-voltage capability and programmable slope control is presented. A digital peak current-mode controller is also integrated with the dual-mode driver. The IC was implemented in a 140-nm automotive bipolar-CMOS-DMOS silicon-on-insulator process. The driver/controller IC is copackaged with an optimized 600-V GaN HEMT fabricated in a GaN-on-Si process. The solution was verified to operate at up to 1 MHz in a 35-W boost converter prototype and achieves a programmable switching-node $dv/dt$ of up to 20 V/ns. To the best of the author's knowledge, this is the first monolithic integration of a cascode MOSFET, device driver, and digital current-mode controller that is designed specifically for high-voltage GaN devices.

Unified Digital Current Mode Control Tuning With Near Optimal Recovery in a CCM Buck Converter

Linear small-signal models of a dc–dc converter often ignore switching dynamics; thus such models are insufficient to fully explore the performance objective under large signal transients. Linear/nonlinear hybrid controllers are promising alternatives; however, they require structurally different hardware resources along with extra antiwindup arrangements. This paper proposes a geometric tuning method in a digitally current-mode-controlled buck converter under continuous-conduction mode. This considers a proportional-integral voltage controller along with a load current feedforward in the digital domain, while the inductor current has a traditional analog implementation. This resembles a first-order switching surface with near load-invariant regulation; thus a (fixed) small integral gain is sufficient to minimize the steady-state error. Using phase-plane geometry, the objective is to tune the controller gain in a way to achieve proximate time optimal recovery using a fixed-frequency pulse-width modulator and also to retain the large-signal stability. The effects of parameter variation and finite sampling are analyzed. The proposed tuning is implemented using an FPGA device.

Merged Flyback–SC-Based Output Stage for Versatile Portable Transcutaneous Electrical Stimulators

This paper introduces a highly flexible multichannel output stage for battery-powered portable electric stimulators (ESs), based on novel power converter architecture. Compared with other solutions, the presented output stage for transcutaneous (surface) stimulations increases the number of applicable therapies, improves the battery operating time through reduced power consumption, and potentially results in more comfortable and shorter healing therapies. The new hybrid switch-mode power converter is a combination of flyback and switched-capacitor (SC) topologies. The flyback steps up the battery voltage and provides galvanic isolation. The following power-efficient SC stage replaces lossy linear current sources (CSs) of conventional solutions and produces pulses with a much higher slew rate, reducing the pulse energy needed to cause the stimulus. The SC also inherently produces pulses with zero-net charge, eliminating bulky blocking capacitors and/or dedicated discharging circuits. The regulation of the amplitudes of the pulses is performed with a new digital voltage-programmed current mode controller, forcing the output of the SC stage to behave as a CS. The flexible digital controller allows for creation of various types of pulses and also features several levels of patient protection. An experimental prototype of the output stage has undergone proof of principle tests with able-bodied individuals. The results show that the new output stage produces pulses with a 1-mA/ns slew rate, about two orders of magnitude higher than the other known solutions. The trials show that the faster slew rate pulses generate the same muscle contraction with 34% lower amplitudes, reducing energy consumption by 55%, allowing longer battery life of portable ES applications.

Digital Sensorless Current Mode Control Based on Charge Balance Principle and Dual Current Error Compensation for DC–DC Converters in DCM

For discontinuous conduction mode (DCM) dc–dc converters with digital sensorless current mode (DSCM) control, an observed current error occurs, owing to a low-accuracy current observer. Moreover, a reference current error occurs due to a low-accuracy current controller or a finite dc gain of current loop. Conventionally, the observed current is compensated to increase current regulation accuracy, whereas the reference current error is neglected. However, for charge balance principle (CBP)-based DSCM (CBP-DSCM) control, this paper proves that the reference current should be compensated in a same quantity to that of observed current. Otherwise, single or unequal compensation leads to output voltage steady-state error. For this reason, a dual current error compensation strategy for CBP-DSCM control is proposed. It compensates the errors in a same quantity through a current error observer, which considers parasitics and calculates the current errors without approximation. To verify the proposed strategy, small-signal models with parasitics for both the converter and the controller are constructed by differential functions of key variables. Furthermore, converter stability is analyzed at typical operation condition, while the stability at various operation conditions is verified through robustness analysis. Finally, simulations and experimental results verify the analysis and the improved transient response of the converter.

Nonlinear Analysis of Discretization Effects in a Digital Current Mode Controlled Boost Converter

Digital current mode control finds wide spread application in point of load power converters in DC nano-grid because of its technical benefits. However, finite current-loop sampling effects introduce undesirable sub-harmonic oscillations. This paper presents an analytical framework to investigate such nonlinear phenomena in a digitally current mode controlled boost converter. Discrete-time models for multi-sampled current loops and uniform sample with compensating ramp are derived under continuous conduction mode. We show that the discrete-time maps for such systems are discontinuous in nature. While the error voltage using a proportional-integral controller stays within the zero-error-bin (ZEB), the reference current becomes constant and 1-D maps of the inner current-loop can be used for stability analysis. Uniform sampling may lead to chaos, period doubling or stable period-1 behavior depending on slope of the compensating ramp. Multi-sampled current loop imposes several borders in the discrete parameter space and may eventually lead to high periodic behavior. In a counter-based compensating ramp, staircase effects may lead to sub-harmonic oscillation. Such instability eventually brings the error voltage outside the ZEB and 2-D map models have to be used for further investigating the nonlinear phenomena. A boost converter prototype was made. Digital current mode control is realized using an FPGA device. Test results demonstrate close agreement with the analysis.

Selectively Sampled Subharmonic-Free Digital Current Mode Control Using Direct Duty Control

Benefits of digital current mode control are often limited by the choice of a current-loop sampling rate. A higher rate requires a fast analog-to-digital converter that consumes substantial power and increases cost. A lower rate often results in subharmonic oscillations, even using a programmable ramp compensation. This brief proposes a simple technique to compute the steady-state duty ratio in real time, when the closed-loop controller is in action. A time-to-digital converter translates cycle-by-cycle duty ratio information into digital code, and a “duty ratio computation” block generates the computed duty ratio using a moving average filter. At steady state, this enforces a virtual open-loop configuration and completely disables current-loop sampling and controller computation, thereby saving substantial power and eliminating subharmonic oscillations. Considering a dc–dc buck converter as the test case, it is found that even in the presence of high periodic behavior under the closed-loop control, a near-ideal steady-state duty ratio can be reconstructed. Design-related issues along with duty ratio saturation are discussed with test cases.

English

This paper presents a elimination of voltage steady-state error and achieve high-accuracy current estimation without using current sensor. The elimination of voltage steady-state error and achieve high-accuracy current estimation purpose using comprehensive compensation strategy. This comprehensive compensation strategy algorithm cannot effectively eliminate the output voltage steady-state error, so fuzzy logic controller is implemented. A digital current-mode controller for dc-dc converters is introduced.The current control mode proposed current observer and PCC algorithm. It achieves the highest observation accuracy by compensating for all the known parasitic parameter. By employing the optimal current observer-based predictive current controller, a boost converter is implemented. The current-mode loop is sensorless, relying on constants and internal loop states. Fast current-mode control mechanism is implemented. This control scheme is that it facilitates the application of a low resolution PWM.

A Digital Parallel Current-Mode Control Algorithm for DC–DC Converters

This paper presents a novel digital current-mode control strategy for dc-dc converters. In the proposed algorithm, the required duty cycle is calculated directly by two parallel terms. With some simple operations in digital implementation, the resultant control system achieves rapid and precise output voltage regulation under the input voltage and output load change. Moreover, the implementation of the proposed algorithm with a digital controller is discussed in detail. Analysis shows that the parallel current-mode control does not exhibit subharmonic oscillation. A 400-kHz switching frequency buck converter based on field-programmable gate array implementation is built to verify the feasibility and advantages of the parallel current-mode control.

A Digital Peak Current-Mode Control PFC with Bifurcation Control

A boost power factor correction (PFC) in continuous conduction mode (CCM) by the digital peak current-mode control method with bifurcation control is discussed in this paper. The proposed method is used to prevent the inductor current bifurcation behavior, which is caused by sub-harmonic oscillation when the duty cycle is upon to 50 percent. The bifurcation behavior will increase the inductor current ripple and dissipation, then reduce the Power Factor (PF). Different from the ramp compensation signal performed with analog IC in some papers, a MCU is used to be the controller and also provides the digital compensation function in this paper. With the timer, ADC, PWM, and comparator which are built in the MCU, the necessary parameters will be measured without extra components and additional cost. The proposed method is based on those parameters. In this paper, the MATLAB/Simulink simulation results show the proposed method workable.

Automatic dimming multi-lamp fluorescent management system with active input power factor corrector stage

This study presents the development and implementation of an automatic multi-lamp lighting fluorescent system, based on electronic ballasts with capacity of ideal programmable preheating and dimming capabilities, and digital average current mode control for the active input power factor corrector stage. Furthermore, the proposed system allows remote monitoring and management through a friendly software platform, which includes light and presence sensors, where the system operates automatically or manually, according to the necessity of each environment and/or final user, allowing an efficient and smart lighting system control.

Predictive Digital Current Control of Single-Inductor Multiple-Output Converters in CCM With Low Cross Regulation

This paper presents a new digital current-mode control technique for single-inductor multiple-output converters in continuous-conduction mode. This predictive control method can calculate all the required duty cycles corresponding to the outputs for the next switching cycle. Since the calculation is based on every current reference representing the load current, all current control loops corresponding to different outputs are theoretically independent, which can greatly reduce the cross regulation. To avoid subharmonic oscillation, proper predictive digital current control is adopted. Inductor current estimation is used to remove the current sensing circuit, and corresponding calibration techniques are presented. Simulation and experimental results are given to verify the effectiveness of this control technique.

Design and Implementation of Fully Integrated Digitally Controlled Current-Mode Buck Converter

Digital current-mode control is a dual-loop control which potentially results in a better transient response and thus is more favorable than voltage-mode control. There are only a few publications on how to design and implement a fully integrated digital controller as the on-chip implementation is very challenging, especially for current-mode control. This paper addresses those design challenges and considerations. One of the main challenges is to efficiently sample and quantize both the output voltage and inductor current of the buck converter for control purposes. A time-multiplex scheme is used for the control-loop which enables the converter to work with a single ADC. A modified delay-lock-loop DPWM has been developed for minimizing the mismatch of the delay-cells. This enhances the accuracy at high frequency to prevent limit-cycle. A new algorithm has also been proposed for implementing look-up-table digital compensators with 20% less chip area. A converter with the fully integrated digitally controlled loop, including the single ADC, digital compensators and DPWM, has been fabricated in a CMOS 0.35 μ m process with a chip area of 1049 μm × 1533 μm. Measurement results show that the buck converter has a load transient response of 20 μs, which is one of the fastest compared to other state-of-the-art digitally controlled buck converter.

Digital Average Current-Mode Control Using Current Estimation and Capacitor Charge Balance Principle for DC–DC Converters Operating in DCM

A new digital average current-mode control technique is proposed for dc-dc converters operation in discontinuous conduction mode. In contrast to the regulation of inductor current, this paper focuses on how the suitable charge current is feed to capacitor and load resistor directly. Using the principle of capacitor charge balance, the charge current reference in next switching cycle is predicted in order to drive the output voltage back to its nominal value quickly during transient conditions. The actual average charge current is estimated from a simplified algorithm, which can also be used to calculate the required duty ratio according to the charge current reference. This control technique features good dynamic performance and it is compliant with the performance constraints of digital integrated processor. The effectiveness of the proposed solution has been proved by the simulation and experimental results.

Digital Average Current-Mode Controller for DC–DC Converters in Physical Vapor Deposition Applications

A dc power supply in physical vapor deposition (PVD) applications operates as a constant power source during normal operation or as a constant current source during fast micro arcs in the plasma. A two-loop control is usually applied: an external (slower) loop controls the output power, while an internal (fast) loop controls the current. This paper introduces a digital average current mode controller for DC power supplies in PVD applications. The controller provides a current source response to fast disturbances, and enables equal current sharing among buck converter modules operating in parallel. Adaptive adjustments of the compensator gain in the digital current control loop enable operation over wide ranges of output power and voltage. The proposed control strategy is robust and noise insensitive. The current and power control algorithms are implemented on a digital signal processor/field-programmable gate array-based digital control platform using a low-cost 10-bit 500 kS/s analog-to-digital converter. The performance is verified on a 25 kW experimental prototype.

マルチフェーズ方式トランスリンク形昇圧チョッパ回路の電流モード制御

Novel current mode control method for the multi-phase trans-linked boost chopper circuit which is suitable for Electric Vehicle (EV), Hybrid Electric Vehicle (HEV) and Fuel-Cell Electric Vehicle (FC-EV) is proposed in this paper. In case of the proposed digital current mode control method suitable for the multi-phase trans-linked type boost chopper circuit, the inductor current is sampled only twice in a switching period. The proposed digital current mode control method needs independent control for each phase current. Furthermore, solving the problem of the current instability effectively, a compensating ramp is required for the current control algorithm. The proposed digital current mode control algorithm and the block diagram are described in this paper. In addition to this, the condition of the compensating ramp for the multi-phase trans-linked type boost chopper circuit is shown, too. The feasible evaluations of the proposed digital current mode control are discussed with the experimental result.