Discrete-Time Framework for Analysis and Design of Digitally Current-Mode-Controlled Intermediate Bus Architectures for Fast Transient and Stability

Abstract

In an intermediate bus architecture (IBA), a buck converter, while driving a constant power load (CPL), exhibits unstable poles in its control-to-output transfer function. This may result in limit-cycle oscillations due to the lack of sufficient damping, and an active damping using current-mode control (CMC) can stabilize the converter. However, existing small-signal stability results are not sufficient to ensure the fast-scale stability of the overall IBA system under digital CMC. This article proposes a discrete-time framework to derive necessary and sufficient stability conditions to meet both small-signal and fast-scale stability requirements of a mixed-signal CMC (MCMC) buck converter driving a CPL. The latter is a point-of-load (PoL) converter driven by MCMC with the switching frequency much faster than that of the former. Design methods are proposed for an enhanced stability boundary followed by a nonlinear controller-tuning method for near-time optimal transient recoveries for both the converters by considering a time-scale separation. A buck converter-based IBA prototype is developed, and analytical predictions are verified using the experimental results.