Analysing the effects due to discontinuous output‐voltage ripple in a digitally current‐mode controlled boost converter

Abstract

Digital implementation of current-mode control (CMC) considers the outer voltage-loop in the digital domain, whereas the inner current-loop is kept either in the analogue domain in mixed-signal CMC (MCMC) or in the digital domain in fully digital CMC (DCMC). Under finite voltage-loop sampling, this study reports that the selection of sampling point can completely change the stability status of a boost converter with non-minimum phase behaviour, particularly in the presence of the effective-series-resistance of the output capacitor. A discrete-time framework is proposed for fast-scale stability analysis in a boost converter, operating under continuous conduction mode. Further, discrete-time small-signal models are derived and design guidelines are proposed for both MCMC and DCMC architectures with enhanced stability for fast transient performance. Keeping in mind software-controlled DCMC, a considerably large sampling delay is considered, and its effect on the performance and stability is discussed. A boost converter prototype is tested and various DCMC schemes along the proposed design techniques are implemented using a field-programmable-gate-array device.