Digital Circuit Design Research Articles

Computational study of bilayer armchair graphene nanoribbon tunneling field-effect transistors for digital circuit design

Computational study of bilayer armchair graphene nanoribbon tunneling field-effect transistors for digital circuit design

Four-Bit Parallel Multiplier based on Digital Circuit Design

This paper presents an investigation into a four-bit parallel multiplier based on an enhanced digital circuit design. The advent of computers and digital electronic systems has led to a significant increase in the importance of multiplication operations in a wide range of applications.In this paper, the circuit is designed using the Logisim, and the designed circuit is converted into a model and input into Modelsim for simulation. Finally, the feasibility of the circuit is verified through the Modelsim model. The objective of the circuit is to implement the multiplication operation of two four-bit inputs. The model designed in Logisim can facilitate the process of code writing in Modelsim simulations. Furthermore, once the simulation is complete, the simulation results can be compared with the circuit diagram to ascertain their alignment with reality. The entire model is based on the concept of a full adder, and the delay is reduced by disconnecting the serial feed chain, which results in a 25% reduction in delay compared to a full adder with two columns. This approach effectively achieves the desired reduction in delay.

Design and Optimization of the 4-Bit Absolute Value Logic Gate Circuits

Absolute value computation of binary numbers has important applications in digital signal processing and arithmetic operations, but conventional circuit designs usually face high latency and energy consumption problems. In order to improve computational efficiency, this paper proposes an optimization method based on logic gate circuits aimed at reducing the number of physical components and simplifying the circuit structure. By using a truth table for logic simplification, a more efficient 4-bit absolute value calculation circuit is designed in this study. Experimental results show that the optimised circuit performs significantly in reducing latency and power consumption and maintains the accuracy of the operation. The results of the study provide a better implementation of digital circuit design for application scenarios that require efficient computation.

DeLoSo: Detecting Logic Synthesis Optimization Faults Based on Configuration Diversity

Logic synthesis tools are the core components of digital circuit design, which convert programs written in hardware description languages into gate-level netlists, and optimize the netlists. However, the netlist optimization is complex, with numerous optimization parameters to be configured. Any minor optimization faults in logic synthesis tools may cause circuit diagrams to significantly deviate from the original design, posing risks in target systems. We propose DeLoSo, the De tector of Lo gic S ynthesis o ptimization faults, the first method specifically designed to identify potential faults in the optimization processes of logic synthesis tools. DeLoSo relies on netlist differences and parameter variations to guide the generation of diverse Logic Synthesis Optimization Configuration (LSOC) combinations to thoroughly test the optimization process. DeLoSo consists of three components: LSOC generator, which generates diverse LSOC combinations through configuration recombination and mutation; LSOC diversity evaluator, which assesses the diversity of optimization configurations; and LSOC validator, which validates the generated LSOC combinations to discover optimization faults. DeLoSo identified 19 faults in two established logic synthesis tools (i.e., Vivado and Yosys); 15 of them have been fixed by vendors. Particularly, the community maintainers of Yosys have considered incorporating DeLoSo into Yosys’ existing test suite.

Innovative Multi-Bit Test Pattern Generators with Variable LFSR Selection Mechanisms

Test Pattern Generators is an important module for testing Asynchronous circuits that guarantee fault detection. In this paper a multi-bit TPGs with tunable LFSR lengths is presented. Our method enables smooth transitions between various word lengths by dynamically selecting LFSR configurations based on control signals. For 4-bit to 7-bit combinational circuits, we have derived a polynomial-based LFSRs and shown effect of stuck-at-fault detections through extensive testing. It includes a discussion of instructional insights regarding fault coverage and digital circuit design. By bridging fixed and flexible BIST solutions, our adaptive TPG design improves fault detection capabilities.

Algorithm prediction of single particle irradiation effect based on novel TFETs

In order to predict the single particle irradiation of tunnel field effect transistor (TFET) devices, a deep learning algorithm network model was built to predict the key characterization parameters of the single particle transient. Computer aided design (TCAD) technique is used to study the influence of single particle effect on the novel stacked source trench gate TFET device. The results show that with the increase of drain voltage, incident width of heavy ions (less than 0.04μm), and linear energy transfer, the drain transient current and collected charge also increase. The prediction results of deep learning algorithm show that the relative error percentage of drain current pulse peak (IDMAX) and collected charge (Qc) is less than 10%, and the relative error percentage of most predicted values is less than 1%. Comparison experiments with five traditional machine learning methods (support vector machine, decision tree, K-nearest algorithm, ridge regression, linear regression) show that the deep learning algorithm has the best performance and has the smallest average error percentage. This data-driven deep learning algorithm model not only enables researchers who are not familiar with semiconductor devices to quickly obtain the transient data of a single particle under any conditions; at the same time, it can be applied to digital circuit design as a data-driven device model reflecting the reliability of single particle transient. The application of deep learning in the field of device irradiation prediction has a highly promising prospect in the future.

Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application

Advances in wearable technology, IoT, and mobile applications have increased the demand for ultra-low-power electronic devices. Adiabatic Logic Circuit (ALC) is a design technique utilized in digital circuits to decrease the power consumption by decreasing the dynamic power dissipation. Current technologies face challenges in achieving both high performance and ultra-low power consumption. This research work introduces a novel approach in digital circuit design, specifically the Gate All-around Carbon Nanotube Field Effect Transistor with Discrepancy Cascode Pass Transistor Adiabatic Logic (GAA-CNTFET-DCPTAL), tailored for ultra-low power applications. This design operates efficiently with a four-phase Power Clock (PC) and demonstrates remarkable performance by achieving operation frequencies of up to 1 GHz while minimizing energy dissipation. GAA-CNTFET provides superior electrostatic control and high carrier mobility, reducing leakage currents and enhancing switching speeds. Simultaneously, Discrepancy Cascode Pass Transistor Adiabatic Logic (DCPTAL) uses adiabatic logic principles and a cascode structure to minimize energy dissipation during switching events. The technology node of proposed model is 10 nm. The software used for assessment is HSPICE is used for the simulation and validation of the proposed design. The proposed GAA-design attains 25.36 %, 14.28 %, and 16.06 % lower average power analyzed with existing techniques, such as Design with Evaluation of Clocked Differential Adiabatic Logic Families for the applications of low Power (DE-CDAL-LPA), Adiabatic logic-base strong ARM comparator for ultra-low power applications (AL-SARM-ULPA) and Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC with Embedded Applications (2PADCL-ULP-VLSI) respectively.

Optimization design and application scenario research of low power digital integrated circuit

Optimization design and application scenario research of low power digital integrated circuit

Investigating the 20T Hybrid Full Adder Design for Low Power and High-Performance Computing

The 1-bit full adder is a crucial building block in digital circuits, widely used in various applications such as arithmetic circuits, digital filters, and computer memory. In this study, a thorough investigation of a novel 1-bit full adder circuits was conducted, covering their design, analysis, and optimization for minimizing their power consumption and delay while maintaining their robustness and functionality. The design also introduces modified XOR and XNOR gates as crucial components. The proposed circuit was simulated using Cadence Virtuoso tool with 90-nm GPDK CMOS technology. To evaluate the proposed adder, comparisons were made with several well-known adder designs based on power consumption, speed, and power delay product. The proposed hybrid full adder improved power delay product by 20.6% to 69.4% and reduced worst-case propagation delay by 16.6% to 63.5% compared to prior designs in the literature. This study's findings offer useful insights into digital circuit design and can contribute to the development of low-power, high-performance full adder circuits.

Parkinson’s neural network modeling and digital circuit design of nucleus

Parkinson’s neural network modeling and digital circuit design of nucleus

The application of Verilog in the development of casual games

Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and intelligence in modern society. As digital technology continues to advance across various industries, the need for effective and dependable digital circuit design languages is also increasing. This paper delves into the complex process of recreating the timeless arcade classic Pac-Man on the Spartan 3E FPGA platform using hardware description and digital circuit techniques and the Verilog programming language. Through a comprehensive review of existing literature and research, this study investigates the fusion of traditional game design principles with state-of-the-art hardware programming methods, demonstrating the seamless integration of software-driven game mechanics with hardware-based implementation. Through careful design and coding strategies, Pac-Man's basic functionality, such as maze traversal, ghost AI, and pellet consumption, is faithfully replicated using Verilog modules customized for the Spartan 3E FPGA board. By bridging the realms of game development and hardware engineering, this paper not only showcases the versatility of Field Programmable Gate Array (FPGA) technology in entertainment applications but also underscores the interdisciplinary nature of modern computing endeavours.

Laboratory work “Digital circuit design and algebra of logic: creation of digital devices in an online simulator”: competence-based approach for the purposes of continuity of education levels

Laboratory work “Digital circuit design and algebra of logic: creation of digital devices in an online simulator”: competence-based approach for the purposes of continuity of education levels

Cascadable-Controllable Self-Assembly DNA Tiles for Large-Scale DNA Logic Circuits.

In the last few decades, DNA-based self-assembly tiles has become a hot field in research due to its special applications and advantages. The regularity and strong design methods comprise other DNA-based digital circuit design methods. In addition to the obvious advantages of this method, there are challenges in performing computations based on self-assembly tiles, which have hindered the development and construction of large computing circuits with this method. The first challenge is the creation of crystals from DNA molecules in the output, which has led to the impossibility of cascading. The second challenge of this method is the uncontrollability of the reactions of the tiles, which increases the percentage of computing errors. In this article, these two challenges have been solved by changing the structure of leading tiles so that without the activator strand, tiles remain inactive and cannot be connected to other tiles. Also, when the tiles are activated, single-strand DNA will be released after connecting to other tiles, which will be used as the output of the circuit. This output gives the possibility of cascading to self-assembly designed circuits. The method introduced in this article can be a beginning for the re-development of DNA-based circuit design with the self-assembly tile method.

Probability Driven Double-Edge Triggered Multibit Flip Flop and Clock Gating Integration

Abstract: The project delves into the using of Double Edge-Triggered Multi-Bit Flip-Flops (DETMBFFs) alongside Data Driven Clock Gating (DDCG) techniques to bolster power efficiency in digital circuit designs. DETMBFFs enable the data Capture on Both Up and Down Swings of a clock, optimizing throughput while conserving power. By grouping multiple flip-flops and employing a shared clock driver, DETMBFFs minimize redundant clock signals and reduce energy usage. The integration of DDCG selectively disables clock signals based on data activity, further enhancing power efficiency. A novel algorithm, grounded in the ratio of the data to clock toggling and probability-driven grouping of flip-flops within DETMBFFs, is developed to optimize power consumption. Through implementation using Xilinx software tool, the combined approach achieves remarkable power savings ranging from 17% to 23%. This creative approach not only enhances power efficiency but also maintains design integrity,making it a compelling solution for low-power design challenges in digital systems.

Comparative performance evaluation of voltage gate-spin orbit torque MTJ-based digital logic circuits with 45 nm CMOS technology

The development of advanced logic systems relies on low-power, compact devices with incredibly fast computational speeds. Voltage gate spin–orbit Torque Magnetic Tunnel Junction has emerged as a prominent solution, meeting these requirements and playing a crucial role in the design of digital circuits. This paper concentrates on the design, implementation, and performance evaluation of gates (AND, OR, XOR) and combinational circuits (2 × 1 Mux, subtractor, and adder) based on VgSOT MTJ. The performance characteristics of these circuits have been evaluated, and comprehensive comparisons have been made with conventional 45 nm CMOS and SOT/STT-based circuit designs. In this paper, based on the latency performance analysis, it has been established that the logic gates and combinational circuits utilizing VgSOT exhibit superior performance of approximately 96% compared to CMOS counterparts. Similarly, latency performance improvement of 44% and 75%, respectively, is seen for VgSOT-based logic gates and combinational circuits over SOT and STT-based circuits. Analysis of power consumption in VgSOT-based logic gates has revealed a remarkable power efficiency of ∼98% over CMOS- and SOT/STT-based circuit implementations. Implementing VgSOT MTJ-based design brings about notable improvements in the performance of different logic designs.

QCA-based fault-tolerant XOR Gate for reliable computing with high thermal stability

The XOR gate is an essential element in the design of digital circuits due to its versatility and usefulness. The design of XOR gate in this paper is based on Quantum-dot Cellular Automata (QCA) 2D planner technology with no line-to-line intersections. The output amplitude is improved by redundant cell-based design, which also helped reliability and fault tolerance outperform. The proposed XOR gate achieves fault tolerance to single-cell addition and missing-cell defects from 68.48% to 95.33%. In addition, the proposed XOR gate is also fault-tolerant against multiple-cell missing defects, as verified from the simulations. Furthermore, high thermal stability makes the circuit reliable for QCA-based digital design applications. The digital design applications such as 4-bit B2G code converter and a 4-bit parity checker are designed from this XOR gate, utilizing 438 and 414 cells, respectively. This demonstrates its effectiveness in designing fault resilient and reliable circuit designs for various applications.

Novel design of cryptographic architecture of nanorouter using quantum-dot cellular automata nanotechnology

The article introduces a revolutionary Nanorouter structure, which is a crucial component in the Nano communication regime. To complete the connection, many key properties of Nanorouters are investigated and merged. QCA circuits with better speed and reduced power dissipation aid in meeting internet standards. Cryptography based on QCA design methodologies is a novel concept in digital circuit design. Data security in nano-communication is crucial in data transmission and reception; hence, cryptographic approaches are necessary. The data entering the input line is encrypted by an encoder, and then sent to the designated output line, where it is decoded and transferred. The Nanorouter is offered as a data path selector, and the proposed study analyses the cell count of QCA and the circuit delay. In this manuscript, novel designs of (4:1)) Mux and (1:4) Demux designs are utilized to implement the proposed nanorouter design. The proposed (4:1) Mux design requires 3–5% fewer cell counts and 20–25% fewer area, and the propsoed (1:4) Demux designs require 75–80% fewer cell counts and 90–95% fewer area compared to their latest counterparts. The QCAPro utility is used to analyse the power consumption of several components that make up the router. QCADesigner 2.0.3 is used to validate the simulation results and output validity.

Design Wallace Tree Multiplier Using Reversible Gates

Abstract: Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree multiplier using reversible gates outperforms traditional multipliers in terms of power dissipation and delay, with values of 0.027W and 29.327nS re­spectively.

Variations in the characteristics of low-voltage logic gates based on vertical silicon nanotransistors with a conical channel

The issues of numerical simulation of fluctuations in the electro-physical characteristics of low-voltage logic gates based on silicon vertical nanotransistors with a surrounding gate with a conical geometry are discussed. Instrumentation and technological models of n- and p-types of conductivity of conical nanotransistors have been developed for the case when the conical working area is set as follows. On the source side, for a large diameter, the condition for suppressing short-channel effects is not fulfilled, and on the drain side, for a small diameter, it is fulfilled. Such transistor structures in the control voltage range from 0 to 0.6 V are characterized by a higher transistor current, a low leakage current and a slope of the subthreshold characteristic close to the theoretical limit. Prototypes of transistors with optimal parameters for the synthesis of logic gates with a gate length of 25 nm and a working area diameter ratio of 8.5/10 nm have been selected. The fluctuation range of the drain current is distributed according to the normal law for both types of transistors with an average of 12.25 µA for the n-type and 6.5 µA for the p-type and a standard deviation of 19.3. The total spread is 3.06 µA and 1.45 µA, or 25% and 22%, respectively. To offset the influence of the considered mechanisms, it is recommended to limit the level of doping of the drain/source regions and use relatively large cross-sections of the working area from the range of possible ones. This will ensure stable electro-physical characteristics of transistors with high parry of short-channel effects. An instrument-technological model of an inverter based on vertically arranged n- and p-type transistors with an optimized diameter ratio has been developed. Variations of electro-physical characteristics in the range of control voltages 0...0.6 V and a clock frequency of 20 GHz are numerically investigated. In all cases, the prototypes demonstrate picosecond delays and low power consumption. The valve model predicts a general fluctuation of switching times of 18% at average values of 1.6 and 0.8 ps, respectively, active power of 16% at an average value of 0.2 µW and static power of 11% at an average value of 0.7 pW. The results of the study can be used in the design of digital circuits to expand the SOA zone.

Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins

Placement is a critical step in the physical design for digital application specific integrated circuits (ASICs), as it can directly affect the design qualities such as wirelength and timing. For many domain specific designs, the demands for high performance parallel computing result in repetitive hardware instances, such as the processing elements in the neural network accelerators. As these instances can dominate the area of the designs, the runtime of the complete design’s placement can be traded for optimizing and reusing one instance’s placement to achieve higher quality. Therefore, this work proposes a mixed integer programming (MIP)-based placement refinement algorithm for the repetitive instances. By efficiently modeling the rectilinear steiner tree wirelength, the placement can be precisely refined for better quality. Besides, the MIP formulations for timing-driven placement are proposed. A theoretical proof is then provided to show the correctness of the proposed wirelength model. For the instances in various popular fields, the experiments show that given the placement from the commercial placers, the proposed algorithm can perform further placement refinement to reduce 3.76%/3.64% detailed routing wirelength and 1.68%/2.42% critical path delay under wirelength/timing-driven mode, respectively, and also outperforms the state-of-the-art previous work.