Comparative performance evaluation of voltage gate-spin orbit torque MTJ-based digital logic circuits with 45 nm CMOS technology

Abstract

The development of advanced logic systems relies on low-power, compact devices with incredibly fast computational speeds. Voltage gate spin–orbit Torque Magnetic Tunnel Junction has emerged as a prominent solution, meeting these requirements and playing a crucial role in the design of digital circuits. This paper concentrates on the design, implementation, and performance evaluation of gates (AND, OR, XOR) and combinational circuits (2 × 1 Mux, subtractor, and adder) based on VgSOT MTJ. The performance characteristics of these circuits have been evaluated, and comprehensive comparisons have been made with conventional 45 nm CMOS and SOT/STT-based circuit designs. In this paper, based on the latency performance analysis, it has been established that the logic gates and combinational circuits utilizing VgSOT exhibit superior performance of approximately 96% compared to CMOS counterparts. Similarly, latency performance improvement of 44% and 75%, respectively, is seen for VgSOT-based logic gates and combinational circuits over SOT and STT-based circuits. Analysis of power consumption in VgSOT-based logic gates has revealed a remarkable power efficiency of ∼98% over CMOS- and SOT/STT-based circuit implementations. Implementing VgSOT MTJ-based design brings about notable improvements in the performance of different logic designs.