Differential Nonlinearity Error Research Articles

A 14-Bit Digital to Analog Converter for a Topmetal-CEE Pixel Readout Chip

The Lanzhou Heavy Ion Research Facility (LIRF) is the largest heavy ion research facility in China, providing a substantial volume of experimental data for fundamental research in nuclear physics. The Topmetal-CEE is a pixel readout chip specifically designed for tracking detectors. Within the Topmetal-CEE framework, the front-end amplifier and comparator necessitate precisely adjustable bias voltages. Hence, in this paper, a 14-bit resolution DAC with an R-2R resistor network structure is designed, along with an amplifier featuring high driving capabilities as the DAC driver, thus preventing potential impedance issues when driving large pixel arrays. Test results demonstrate that the DAC module, operating under a 3.3 V supply voltage, can consistently output voltages ranging from 0 to 1.8 V. Furthermore, the differential non-linearity error is less than 1.07 LSB, and the integral non-linearity error is less than 1.57 LSB.

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.

A High-Resolution TDC Design Based on Multistep Fine Time Measurement by Utilizing Delay-Adjustable Looped Carry Chains on FPGAs

High-resolution and multi-channel time-to-digital converters (TDCs) are needed in many electrical application systems. A new multi-step fine time measurement method is proposed in this work, which is based on the delay-adjustable looped carry chains to obtain both high resolution and measurement precision. Each sub-step of the fine time measurement is assigned with a different measurement resolution in the descending order by dynamically configuring the delay line length. The time residue to be measured in the following sub-step becomes smaller, so that a finer resolution can be chosen. The overall oscillation number is the summation of the oscillation number of each sub-steps. The resolution of the TDC is determined by the last sub-step. So both high resolution and small oscillation number (corresponding to high measurement precision) can be obtained. The TDC circuit was implemented on Stratix III FPGA chip. Test results showed that the obtained resolution was less than 10 ps, and the measurement precision root mean square (RMS) was about 13 ps. The differential nonlinearity (DNL) error and the integral nonlinearity (INL) error were in the range of -1 least significant bit (LSB) to 1 LSB without any bin calibration. The resource cost per TDC channel includes the lookup table (LUT) cost of 1064 and register cost of 318. The obtained TDC is comprehensively good considering its low resource cost and high linearity, and it is promising for multi-channel TDC design.

An integrated 2-bit all optical analog to digital converter based on photonic crystal semiconductor optical amplifier

In this paper, by integrating InP/InGaAsP/InP Photonic crystal semiconductor optical amplifier (PhC-SOA) with photonic crystal channel drop filters (PhC-CDF), we present a novel fully integrated ultra-small low-power all-optical analog to digital converter (AO-ADC). The self-phase modulation in the PhC-SOA can shift the frequency of the Gaussian input pulse. The two output PhC-CDFs are designed in a way that appropriately codes the frequency-shifted pulse by the PhC-SOA, which consequently converts them to four desired digital output levels. The numerical results indicated that the center wavelength of an amplitude modulated Gaussian pulse with a center wavelength of 1551.228 nm, temporal pulse-width of 10.6 ps, and energy of 74.4 fJ can be shifted by 1.652 nm. This shift is accommodated by utilizing a PhC-SOA with a length of 9 µm and an injection current of 6.5 mA. The shifted pulse is then quantized and coded to the four digital levels of (00, 01, 10, 11) by two point-defect PhC-CDFs. The PhC-CDFs minimize the AO-ADC integral and differential nonlinearity (INL/DNL) errors by compensating for the effect of the nonlinear frequency shift induced by PhC-SOA. The proposed design offers a footprint of 142 µm2 AO-ADC working at 10 Gs/s.

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

PurposeThe purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.Design/methodology/approachAn op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2.FindingsMeasured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.Originality/valueThe experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

On‐chip tunable Memristor‐based flash‐ADC converter for artificial intelligence applications

This study presents a novel hybrid memristor (MR)-complementary metal–oxide–semiconductor-based flash analogue-to-digital converter (ADC). The speed and efficiency of the ADC are important aspects that can significantly affect the overall system performance. The flash ADC is considered the fastest type of ADCs; however, its performance is affected by the resistor mismatch. The proposed flash ADC is the first to use tunable MR to replace conventional resistor to generate accurate reference voltages. This is achieved by utilising the highly analogue behaviour observed in multi-state MR devices fabricated and tested by the authors' group. The electrical parameters of the devices have been extracted by device characterisation, then the voltage-threshold adaptive model (VTEAM) has been used to develop a correlated mathematical and Simulation Program with Integrated Circuit Emphasis (SPICE) device model. The proposed MR-based flash-ADC design solves the issue of resistor mismatch that results in encoding errors by the ability to tune the MR resistance value post-processing. Moreover, being a nanoscale component, the usage of MR significantly improves the area efficiency of the target ADC. Furthermore, the proposed design has improved the ADC transfer function characteristic and has lower differential non-linearity and integral non-linearity errors compared with the conventional design.

A 9 Bit, 3.6 ps Resolution Pipeline Time-to-Digital Converter

This paper describes a 9-bit time-to-digital converter (TDC) with 3.6 ps resolution. The resolution of 3.6 ps is achieved using coarse and fine structure. The structure of the proposed two-step pipeline TDC is composed of a 4-bit coarse TDC (CTDC) based on delay line and a 5-bit fine TDC (FTDC) based on an SAR-CD algorithm where a Time Amplifier (TA) is used between them. Since TA amplifies the time intervals in different stages of delay line to achieve accurate gain with wide linear range. Therefore, the TDC has good linearity. The proposed TDC has Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) errors of 1.6 and 2.6 LSB, respectively. This TDC was designed in 0.18[Formula: see text][Formula: see text]m CMOS technology. Using a supply voltage of 1.8[Formula: see text]V, the proposed TDC consumes 1.88[Formula: see text]mW at 25 MS/s throughput.

Design and Simulation of 4-Bit Flash Analog to Digital Converter (ADC) for High Speed Applications

Objective: To design 4-bit flash Analog to Digital Converter (ADC) for high speed applications. The objectives of the project are to design sample and hold circuit, high efficient DAC circuit, to design a high speed, low power and minimum delay CMOS comparator and thermometer to binary code convertor logic. Methodology: The main block of flash ADC is designing of comparator. For high speed applications Flash ADC requires comparator having high sensitivity and low power dissipation. In this we have used CMOS comparator with cascaded stages, each stage will help in increasing gain and sensitivity and reducing the all types of noises. First stage is the pre-amplifier stage whose output is given to the input of decision stage. Decision stage is followed by post-amplifier stage. Findings: In most papers for designing flash ADC they used dynamic comparator, these dynamic comparators are more difficult to design and will give more power dissipation. In our design we used CMOS comparator with cascaded stages, this type of comparator provides less power dissipation, less delay and high sensitivity by reducing the noise like kickback noise, offset voltages etc. The design is simulated in 180 nm Technology with Cadence Virtuoso Tool and LT spice. Designed comparator has Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) error considered for design within +/- 0.5LSB. For N-bit flash ADC we have 2N-1 comparators, whose outputs will generate patterns of 0’s and 1’s in form of thermometer code; in order to convert it into binary format we have used mux encoder. This mux encoder logic reduces area and very easy to design compared to other methods. Applications/ Improvements: Flash ADC’s are used in various applications ranging from radar receivers, digital sampling, and LAN interface. The proposed design achieved a power dissipation of 0.121 mW with delay of 19.4 ns. The comparator block is designed and simulated. The sensitivity of the comparator is 0.003V. Keywords: CMOS Comparator, DNL and Binary Code Converter, Flash Analog to Digital Converter (ADC), Integral NonLinearity (INL)

A Layout Technique to Reduce the Impact of Parasitic Capacitors Within A Capacitor Array on the Nonlinearity of Data Converters

SAR ADC has a moderate speed, Low area and low cost compared to other ADC implementations. The accuracy expected from a commercial SAR ADC is very high and research has been going on for many years to improve the accuracy. The Linearity of the data converters is the key for accuracy. The Integral nonlinearity and differential nonlinearity errors of data converters are governed by the matching of the unit capacitors/resistors with in capacitor/resistor array. Layout of these arrays can add significant parasitics affecting the nonlinearity of data converters. This paper presents a layout technique to reduce the impact of the parastics on data converter’s nonlinearity.

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators

Calibration is preferred over dynamic element matching (DEM) techniques to correct nonlinearity in digital-to-analog converters (DACs) in high-speed multi-bit continuous-time (CT) delta-sigma modulators (DSMs) to avoid introducing extra excess loop delay. The state-of-the-art calibration techniques, however, involve substantial external control, making it difficult for a complete on-chip realization. In this paper a highly automated on-chip technique for calibrating differential nonlinearity (DNL) and inter-symbolinterference (ISI) errors of a multi-bit DAC in a CTDSM is presented. The proposed technique implements a Calibration Control System (CCS), equipped with a Finite State Machine (FSM) logic, that automates the entire calibration process with minimal intervention. The calibration loop utilizes the modulator itself to produce the digital estimates of the DNL and the average ISI errors of each unit element of the DAC. These digital estimates are then used to configure auxiliary DACs for correction of the errors in the main DAC. For every unit element in the main DAC, an 8-bit dynamic auxiliary DAC injects a calibrated compensation current in the loop at every up-transition of the input data to cancel the average ISI error, and a 5-bit constant current source array corrects its DNL error. Design considerations and post-layout simulation results for a 50-MHz bandwidth, 1.8GS/s 4 th -order CTDSM are presented. The modulator has a 4.8 dB and a 10.8 dB improvement in SNDR and SFDR respectively with calibration, leading to a dynamic range of 71 dB with a total power consumption of 37.7 mW from 1.3 V and 1 V supplies.

A high-linearity time-to-digital converter based on dynamically delay-adjustable looped carry chains on FPGAs.

Time-to-digital converters (TDCs) act as the core component in many scientific and engineering systems which are based on high-accuracy time measurement. Traditionally, field programmable gate array (FPGA) based TDCs are constructed by organizing carry chains in the tapped delay line style, though acquiring high resolution, the differential nonlinearity (DNL) error is high in the range of 2 least significant bits (LSBs)-4 LSBs. Additionally, their long used length of the carry chain costs rather high resource, which is not friendly for multi-channel TDCs. This paper proposes a new TDC architecture based on dynamically delay-adjustable looped carry chains, which works in the Vernier mode. The TDC contains two looped carry chains, and their oscillation period difference (resolution) is dynamically adjusted by a personal computer program without manual intervene and re-compilation of the TDC circuit. A prototype TDC implemented on a Stratix III FPGA obtains the resolution of 26 ps and the DNL less than 1 LSB, but it only uses two carry chains of length of 32 each. The proposed TDC architecture opens a new way to exploit the capability of the carry chains on FPGAs for high-performance TDC applications.

A 10-Bit Self-Clocked SAR ADC With Enhanced Energy Efficiency for Multi-Sensor Applications

This paper presents a 10-bit self-clocked successive approximation analog-to-digital converter (SAR ADC) with enhanced energy efficiency suitable for multi-sensor applications. An automatic algorithm switching scheme possessing the high power efficiency advantages of both LSB-first SA and binary search algorithm is built with detecting the digital interval between two adjacent samplings to anticipate the switching scheme for subsequent sampling. To avoid the requirements for oscillator and clock generator, a self-clock circuit based on asynchronous timing is proposed, which can also serve as a sensor system clock. Furthermore, partial clock jitter compensation technology is added to compress the peak-to-peak jitter. The concepts of self-clock and full dynamic range high power efficiency make the SAR ADC well suited to sensor applications. Implemented in $0.18\mu \text{m}$ 1P6M CMOS process, the proposed ADC generates a 1.99-MHz clock signal with a peak-to-peak jitter of no more than 47.45 ps and achieves an SNDR of 57.7 dB and an SFDR of 68.9 dB with a 494.14-kHz sinusoidal input. The power dissipation is less than $9.3~\mu \text{W}$ , corresponding to a figure of merit 7.5fJ/conversion step. The peak differential nonlinearity error is less than +0.22/−0.27 LSB and the peak integral nonlinearity error is no more than +0.52/−0.55LSB.

An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

A new time-to-digital converter (TDC) with high resolution and high precision is designed and tested in this paper. The converter is realized by combining coarse clock counter with a two-stage delay-line loop shrinking interpolator (DLLSI) based on Vernier configuration, and its prototype has been implemented in a low-cost flash field-programmable gate array device SmartFusion A2F200M3F (Actel). Delay-line loops are used to achieve differential Vernier delay unit and directly shrink the time interval. In order to improve the resolution, decrease measurement time, and diminish the jitter of the cyclic pulse, a two-stage DLLSI method is proposed. The first-stage interpolator rapidly shrinks the measured time interval with low resolution, and the second-stage interpolator determines the final fine resolution. The resolutions are dependent on the entire delay time differences between two delay-line loops of each interpolator. The optimal resolutions are theoretically calculated, and statistic code density test is used to estimate the resolution of the implemented TDC. The implemented two-stage DLLSI has achieved 8.5-ps resolution with 42.4-ps standard deviation and 10-ns dynamic range. The maximum integral and differential nonlinearity errors are less than 7.8 and 3.1 ps.

A 0.66erms− Temporal-Readout-Noise 3-D-Stacked CMOS Image Sensor With Conditional Correlated Multiple Sampling Technique

This paper presents a sub-electron temporal readout noise, 8.3 Mpixel and 1.1- $\mu \text{m}$ pixel pitch 3-D-stacked CMOS image sensor (CIS). A conditional correlated multiple sampling (CMS) technique is introduced to selectively reduce the dark pixel noise by using a full-range ramp and a small-range ramp. In this way, a sub-electron temporal readout noise CIS is achieved without degrading the frame rate dramatically, compared to the conventional CMS method. A column-parallel single slope ADC with dark pixel detection function is proposed as well. A dynamic-dark-signal-region detection technique is used to mitigate differential nonlinearity (DNL) errors due to ramp slope mismatch. The implemented prototype in 45-nm CIS/65-nm CMOS occupies an area of 35.89 mm2. This paper achieves a 0.66erms− with 5-time sampling at a frame rate of 7.2 frames/s, which corresponds to a sample-rate frequency of 36.1 kHz for the column ADC. The DNL (11 b) is improved from +0.98 LSB/−0.94 LSB to +0.29 LSB/−0.39 LSB by using dynamic dark-signal region technique. The figure of merit of this paper is 2.02 nVrms/Hz.

An energy spectrum smoothing algorithm based on TCC-DEE

A smoothing algorithm for energy spectrum based on differential nonlinearity (DNL) error elimination with total counts conservation for high-energy particle detector systems is presented. It is physics based and is only determined by the DNL error of analog-to-digital converter device itself. From the experimental results, this algorithm slightly improves both noise performance and energy resolution, while greatly reduces the testing errors by almost a half compared to their original values. In addition, the reduced- $$\chi ^2$$ statistic for evaluating the Gaussian fitting goodness is significantly reduced by almost two orders after smoothing. As a typical verification example, this algorithm is successfully applied in the ground calibration of the Low Energy X-ray Instrument onboard the Hard X-ray Modulation Telescope (HXMT-LE) satellite, lending it a powerful, nondestructive and low-cost tool for both calibration and data processing for high-energy particle detector systems.

High Temperature Data Converters in Silicon Carbide CMOS

This paper presents an 8-b digital to analog converter (DAC) and 8-b analog to digital converter (ADC) for high-temperature applications. The pair of data converters were designed in a 1.2- $\mu \text{m}$ silicon carbide CMOS process and have been tested from 25 °C to 400 °C. At 400 °C, the DAC has a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) error of 1.2 least significant bit (LSB) and 2.7 LSB, respectively, while the offset and the gain error are 5.9 and 2.7 LSB. The ADC has a maximum DNL and INL error of 3.6 and −3 LSB, respectively, while the offset error is −7 LSB and the gain error is 2.6 LSB. The ADC has an SNDR = 32.15 dB and effective number of bits = 5.05 b at 300 °C. The DAC is the first of its kind in silicon carbide CMOS, while the ADC is the first reported at temperatures over 300 °C.

An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications.

Power consumption is one of the key design constraints in biomedical devices such as pacemakers that are powered by small non rechargeable batteries over their entire life time. In these systems, Analog to Digital Convertors (ADCs) are used as interface between analog world and digital domain and play a key role. In this paper we present the design of an 8-bit Charge Redistribution Successive Approximation Register (CR-SAR) analog to digital converter in standard TSMC 0.18μm CMOS technology for low power and low data rate devices such as pacemakers. The 8-bit optimized CR-SAR ADC achieves low power of less than 250nW with conversion rate of 1KB/s. This ADC achieves integral nonlinearity (INL) and differential nonlinearity (DNL) less than 0.22 least significant bit (LSB) and less than 0.04 LSB respectively as compared to the standard requirement for the INL and DNL errors to be less than 0.5 LSB. The designed ADC operates at 1V supply voltage converting input ranging from 0V to 250mV.

A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications

This paper presents an 8-bit low-power clock gated successive approximation analog to digital converter (SA-ADC) using D-flip flop (D-FF) unit for biomedical applications. The architecture of the proposed SA-ADC is implemented using the sample and hold (S/H) circuit which is based on a sampling transistor with dummy switch, double-tail dynamic latched comparator, the traditional binary weighted capacitor array single ended DAC and a modified clock gated successive approximation register (SAR) controller logic. The SAR controller is implemented using D-FF. The layout and extraction of the proposed low-power clock gated SA-ADC using D-FF unit are done using L-edit and simulated using 90nm CMOS technology file on LT-spice-IV. According to the simulation results, the low-power clock gated SA-ADC using D-FF unit consumes 200nW from 1V power supply without additional calibration or analog circuits. It has signal-to-noise ratio (SNR) of 53.8dB, peak spurious-free dynamic range (SFDR) of 54.2dB, and a signal-to-noise-and distortion ratio (SNDR) of 48dB for a 250Hz full scale input sine wave. It has also an effective number of bits (ENOB) of 7.6-bits, and a figure of merit (FOM2) of 0.1 pJ/Conversion-step. It achieves +0.34/−0.3 and +0.79/−0.58 of Differential non-linearity (DNL) and integral non-linearity (INL) errors respectively. Furthermore, the low-power clock gated SA-ADC using D-FF unit consumes 88.76nW from 0.85V power supply without additional calibration or analog circuits. With 0.85V supply voltage, it has SNR, SFDR and SNDR of 54.6dB, 39.19dB and 37.92dB respectively for the same input sinewave. It achieves ENOB of 6-bits with (FOM2) of 0.13 pJ/Conversion-step. It has DNL and INL of +0.38/−0.28 LSB and +0.9/−0.85 LSB respectively. The digitized of real recorded beta EEG signal is precisely reconstructed by the proposed SA-ADC.

An 8-Bit Unified Segmented Current-Steering Digital-to-Analog Converter

In this paper, an 8-bit segmented current-steering digital-to-analog converter (DAC) is presented where the digital and analog parts are unified using current mode binary to thermometer decoder, resulting in a smaller chip area and simple layout scheme. In addition, the latch and driver circuits which are the main blocks of conventional current-steering DACs are eliminated in this design. Thus, the number of transistors in the digital part of DAC is reduced and higher sampling rate is obtained. Furthermore, the proposed current mode decoder has lower output voltage variation and consequently lower dynamic power dissipation. Finally, the proposed DAC is simulated in 0.18 μm CMOS technology with the 1.8 V supply voltage. The post-layout simulation results show that differential nonlinearity and integral nonlinearity errors are 0.034 and 0.024 LSB, respectively. In addition, the spurious-free dynamic range is 51 dB over 94 MHz output bandwidth at 500 MS/s. Moreover, the total power dissipation of the designed DAC is only 5.7 mW and the active area is small equal to 0.02 mm2.

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

This paper investigates a novel cyclic time-to- digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digi- tizing the time interval between the rising edges of two input signals (Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitiv- ity to temperature, power supply and process (PVT) varia- tions. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. This converter also improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC re- duces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM). In this converter, the inte- gral nonlinearity (INL) and differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the pro- posed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theo- retical and simulation results confirms the benefits of the proposed TDC.