A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications

Abstract

This paper presents an 8-bit low-power clock gated successive approximation analog to digital converter (SA-ADC) using D-flip flop (D-FF) unit for biomedical applications. The architecture of the proposed SA-ADC is implemented using the sample and hold (S/H) circuit which is based on a sampling transistor with dummy switch, double-tail dynamic latched comparator, the traditional binary weighted capacitor array single ended DAC and a modified clock gated successive approximation register (SAR) controller logic. The SAR controller is implemented using D-FF. The layout and extraction of the proposed low-power clock gated SA-ADC using D-FF unit are done using L-edit and simulated using 90nm CMOS technology file on LT-spice-IV. According to the simulation results, the low-power clock gated SA-ADC using D-FF unit consumes 200nW from 1V power supply without additional calibration or analog circuits. It has signal-to-noise ratio (SNR) of 53.8dB, peak spurious-free dynamic range (SFDR) of 54.2dB, and a signal-to-noise-and distortion ratio (SNDR) of 48dB for a 250Hz full scale input sine wave. It has also an effective number of bits (ENOB) of 7.6-bits, and a figure of merit (FOM2) of 0.1 pJ/Conversion-step. It achieves +0.34/−0.3 and +0.79/−0.58 of Differential non-linearity (DNL) and integral non-linearity (INL) errors respectively. Furthermore, the low-power clock gated SA-ADC using D-FF unit consumes 88.76nW from 0.85V power supply without additional calibration or analog circuits. With 0.85V supply voltage, it has SNR, SFDR and SNDR of 54.6dB, 39.19dB and 37.92dB respectively for the same input sinewave. It achieves ENOB of 6-bits with (FOM2) of 0.13 pJ/Conversion-step. It has DNL and INL of +0.38/−0.28 LSB and +0.9/−0.85 LSB respectively. The digitized of real recorded beta EEG signal is precisely reconstructed by the proposed SA-ADC.