Dielectric Liner Research Articles

Modeling, design, and optimization of a dielectric elastomer acoustic liner

The modeling, design, and optimization of an embedded dielectric elastomer (DE) membrane acoustic liner is considered. The acoustic impedance of the liner is modified when the DE is subjected to voltage, resulting in a reduction of the in-plane stress. A lumped element model of an embedded dielectric elastomer acoustic liner is derived and validated in a normal incidence impedance tube and is subsequently used to optimize its performance. The optimization cost functions include (1) maximization of the average absorption coefficient over a targeted frequency range, 400 – 1600 Hz and (2) maximization of the change in the liner fundamental resonance frequency when the membrane is activated. Good agreement between measured and predicted absorption is observed. Tuning of the resonant frequency requires a numerical solution for resonance using the imaginary part of the impedance, since a simple analytical expression for resonance cannot be derived due to the complex coupling between the acoustics of the liner and the electro-mechanics of the DE membrane. Nonetheless, resonant frequency shifts predicted with the lumped element model compare favorably to those measured with the activated liner sample, with a shift of 213 Hz.

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

This review investigates the measurement methods employed to assess the geometry and electrical properties of through-silicon vias (TSVs) and examines the reliability issues associated with TSVs in 3D integrated circuits (ICs). Presently, measurements of TSVs primarily focus on their geometry, filling defects, and the integrity of the insulating dielectric liner. Non-destructive measurement techniques for TSV contours and copper fillings have emerged as a significant area of research. This review discusses the non-destructive measurement of contours using high-frequency signal analysis methods, which aid in determining the stress distribution and reliability risks of TSVs. Additionally, a non-destructive thermal detection method is presented for identifying copper fillings in TSVs. This method exploits the distinct external characteristics exhibited by intact and defective TSVs under thermoelectric coupling excitation. The reliability risks associated with TSVs in service primarily arise from copper contamination, thermal fields in 3D-ICs, stress fields, noise coupling between TSVs, and the interactions among multiple physical fields. These reliability risks impose stringent requirements on the design of 3D-ICs featuring TSVs. It is necessary to electrically characterize the influence of copper contamination resulting from the TSV filling process on the reliability of 3D-ICs over time. Furthermore, the assessment of stress distribution in TSVs necessitates a combination of micro-Raman spectroscopy and finite element simulations. To mitigate cross-coupling effects between TSVs, the insertion of a shield between them is proposed. For efficient optimization of shield placement at the chip level, the geometric model of TSV cross-coupling requires continuous refinement for finite element calculations. Numerical simulations based on finite element methods, artificial intelligence, and machine learning have been applied in this field. Nonetheless, comprehensive design tools and methods in this domain are still lacking. Moreover, the increasing integration of 3D-ICs poses challenges to the manufacturing process of TSVs.

Design and modeling of novel TSV for ternary logic applications

In this paper presents the TSVs are made of conducting material which is implanted in silicon substrate with dielectric liner coated around the metal line. The study of ternary logic signal propagation in through silicon vias is more important since the ternary signals have small noise margins. Moreover, due to the crosstalk noise the fault switching probability is increases in logic circuits. In this work, a novel TSV structure named as metal semiconductor TSVs for the propagation of ternary logic signals has been proposed. Using the proposed model, the probability of occurring the fault tolerance has been reduced and also the performance is enhanced. The proposed model is developed with an analytical RLGC model where the parasitic values are extracted from electromagnetic field solvers. The simulation results of proposed structures are compared with conventional metal–insulator-semiconductor TSVs to show improvements.

Analysis of Crosstalk Effects for Ternary Logic MWCNT Bundled Through Silicon Vias

This article presents a technique to improve the crosstalk effects in ternary coupled through silicon vias (TSVs). The effects of crosstalk are investigated in TSVs using multi walled carbon nanotube (MWCNT) as metallic liner and polymers such as polyimide, polypropylene carbonate (PPC), benzocyclobutene (BCB) as dielectric liners. The circuit model for coupled TSVs driven by ternary inverter is utilized to analyze the various crosstalk issues. The HSPICE tool is utilized to develop the proposed TSVs. The crosstalk issues for the MWCNT TSVs are investigated and compared to single walled CNT (SWCNT) TSVs. Moreover, the power, power delay product (PDP) and energy delay product (EDP) are analyzed and compared to SWCNT TSVs. All the performances are also studied for different TSV pitches. The coupled TSVs with BCB show high performance for the large pitch values. Moreover, it is noticed that the coupled TSVs with BCB at 5000 μm TSV pitch improved the performance up to 40.03% over the SWCNT TSVs.

Performance Enhancement of an MTL Coil Loaded With High-Permittivity Dielectric Liner for 7 T Brain MRI

In a multi-element microstrip transmission line (MTL) transmit array coil, the transmit field ( $B_{1}^{+}$ ) distribution is inhomogeneous due to its standing-wave nature, and the interference effects can severely degrade the $B_{1}^{+}$ and imaging. Therefore, to improve the homogeneity and strength of $B_{1}^{+}$ , this study focuses on the development of a multi-element MTL transmit array coil integrated with a dielectric liner (DL) material. Furthermore, the transmission efficiency ( $T_{x,eff}$ ) is improved in the head region. An eight-element MTL transmits array head coil is investigated using thinner DLs, and the optimized dimensions of the DL are found from its resonant mode at 7 Tesla (T). Simulations and measurements are performed with an MTL transmit array coil at 7 T, and the performance is analyzed for the DL positions and dimensions. Remarkably, the proposed DLs-integrated transmit array coil system offered significant improvements in the $T_{x,eff}$ at different DLs positions. Compared to the case without the DL, the $T_{x,eff}$ is improved by 9% (DL close to the head model), 15% (DL at center), and 39% (DL close to the RF coil). Interestingly, the DL acts as an efficiency tuner element exhibiting a 9% to 39% $T_{x,eff}$ tuning range of improvement. In addition, the RF-shimming technique improves the $B_{1}^{+}$ homogeneity and $T_{x,eff}$ of the coil with DLs by 21% and 42%, respectively, compared to the case without the DL. Moreover, the specific absorption rate (SAR) analysis of the MTL transmit array coil with the DLs is performed. The peak 10g-averaged SAR is reduced from 3.1 W/kg to 2.13 W/kg in the head using DLs and RF-shimming technique. Finally, we used the bench measurement setup to obtain the measured magnetic field. The proposed work exhibits salient features with a smaller DL size and multi-element MTL transmit array coil than other proposed works.

RC Benefits of Advanced Metallization Options

We address RC scaling trends and predict the performance benefits of advanced metallization options with respect to conventional Cu/low- ${k}$ interconnects. The range of interconnect dimensions we cover spans from the 22 nm to the 3 nm logic technology node. We show that Ru and Co fills can significantly reduce resistance at narrow pitches. At 12 nm half-pitch, line and via resistance can be lowered by up to 36% and 75%, respectively, by replacing Cu with barrierless Ru fill; by using hybrid Cu metallization with Co via-prefill, at 12 nm half-pitch via resistance can be lowered by up to 42% in 87° tapered vias and up to 52% in chamfered vias. As far as capacitance is concerned, Ru fill can enable interconnect schemes without dielectric liner. In this case, the line capacitance can be substantially reduced by using linerless replacement low- ${k}$ or air-gap schemes, whose benefits become more significant at narrow pitches, when one accounts for low- ${k}$ sidewall damage in conventional low- ${k}$ schemes and takes these as a reference.

Terahertz radiation emission using plasma-filled dielectric liner with the effects of pre-modulated relativistic electron beam

Terahertz radiation emission using plasma-filled dielectric liner with the effects of pre-modulated relativistic electron beam

Elimination of Scallop-Induced Stress Fluctuation on Through-Silicon-Vias (TSVs) by Employing Polyimide Liner

3-D modeling of through-silicon-via (TSV) with sidewall scallops, combined with an element birth and death technique, is explored in finite-element analysis (FEA) in this paper to evaluate and improve the thermo-mechanical reliability. Compared with the classic FEA, the proposed modeling and simulation method takes into account the process sequence and, hence, can accurately characterize the stress distribution and fluctuation phenomenon of TSVs, which agrees pretty well with X-ray experimental data. In order to solve the stress fluctuation problem, the process-friendly polyimide dielectric liner is employed to replace the SiO2 liner, which smoothens the sidewalls, reduces the average stress values, and eliminates the local stress fluctuation. The average stress on TSVs with a polyimide liner along the silicon-liner interface and copper-barrier interface are both lower than TSVs with an SiO2 liner and the fluctuation magnitude is also dramatically decreased, which demonstrates that the TSV with a polyimide liner has higher reliability and lower risks in interfacial delamination. Furthermore, the keep-out zone size is also decreased by using a polyimide liner, which is beneficial to realize high-density 3-D integration.

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

Optimal-permittivity Dielectric Liners for a 4.7 T Transceiver Array

Placing dielectric pads adjacent to the imaging region is an effective method to increase the signal locally and also increase the radio frequency magnetic field homogeneity in magnetic resonance imaging. The use of local high permittivity pads is becoming more common, and this work focuses on the effect of larger dielectric pads on the transmit/receive performance of an array (e.g., coupling, efficiency and safety) having 8 channels, used to image a cylindrical phantom at 4.7T (200MHz). We investigate the effects of a dielectric liner surrounding the whole volume of interest both with and without an air gap. The simulations reveal that high permittivities are not recommended because they substantially degrade the longitudinal homogeneity, resulting in hot spots of specific absorption rate at the driven end of the array. Furthermore, high permittivities lead to dielectric resonances in the liner at frequencies close to the Larmor frequency, potentially degrading the performance of the array. Indeed, simulations and measurements confirm that a compromise must be made between improvements in field homogeneity and transmit performance, and that an optimal permittivity exists which is much lower than those commonly used in the literature. The optimal permittivity achieves minimal coupling (<−23dB) between array elements, exhibits an intrinsic electromagnetic impedance equal to the geometric mean of those of the coil former and phantom and can be realized with inexpensive materials. For this permittivity the performance with an air gap of thickness equal to that of the liner is equivalent to that without the air gap.

High-Frequency Characterization of Through-Silicon-Vias With Benzocyclobutene Liners

This paper presents design, fabrication, and high-frequency characterization of through-silicon-vias (TSVs) with benzocyclobutene (BCB) as the dielectric liner to exploit its low dielectric constant. Fabrication processes for BCB polymer liner TSVs are developed, and BCB-liner TSVs have been successfully fabricated in both low-resistivity silicon and high-resistivity silicon substrates for comparison. A de-embedding method that enables extraction of S-parameters from cascade TSV chains is developed based on the thru-reflect-line calibration algorithm, and the S-parameters of BCB-liner TSVs have been obtained from the measured transmission properties of cascade TSV chains with frequencies up to 25 GHz. Measurement results show that the BCB liner improves transmission properties of TSVs up to 10 GHz compared with SiO2-liner TSVs, and sub-strate resistivity dominates transmission properties for frequencies higher than 10 GHz.

Design and Large-Signal Modeling of a $W$ -Band Dielectric TWT

The performance capabilities of a dielectric traveling-wave tube (TWT), designed for operation near 94 GHz near the 100-W power level, are investigated using large-signal simulations. Key design elements include a dielectric liner with a moderately high dielectric constant of 13.5, consistent with magnesium orthotitanate ceramic, and the use of a solid round electron beam with properties (26-kV, 100-mA, and 0.185-mm beam radius) that are comparable to those employed in W -band coupled-cavity TWTs. The optimal simulated performance, computed assuming a 5-cm beam-wave interaction length, is 115 W of output power at 94 GHz, with 6-GHz half-power bandwidth, 10.3-dB large-signal gain, and 4.4% electronic efficiency. Technical issues, including the existence of a higher linearity Crestatron regime, the mitigation of beam charging, and thermal management, are discussed.

Control of Mutual Coupling in High-Field MRI Transmit Arrays in the Presence of High-Permittivity Liners

In high-field magnetic resonance imaging, transmit arrays and high-permittivity inserts are often used together to mitigate the effects of RF field inhomogeneities due to short wavelength. However, array performance is limited by mutual impedance between elements which must be closely spaced around the volume of interest. Mutual impedance plays a substantial role at high frequencies and is increased by the presence of dielectric pads which are used to increase the homogeneity of the RF magnetic field. This paper describes a decoupling strategy for an eight-channel transmit/receive array in the presence of a high permittivity dielectric liner. The elements are decoupled using capacitive bridges between adjacent elements. In spite of the higher mutual impedance due to the liner, both mutual resistance and reactance can be removed between adjacent elements (isolation better than 30 dB), and coupling between nonadjacent elements is maintained below 15 dB. The effects of decoupling on the transmit performance of the array in presence of high permittivity liners are investigated in terms of coupling, magnetic field intensity, SAR and transmit efficiencies.

Airgaps in nano-interconnects: Mechanics and impact on electromigration

In this study, electromigration (EM) of interconnects (90 nm pitch) with airgaps was investigated using a combination of computational mechanics, analytical modelling, and EM experiments. EM experiments reveal that airgapped Cu lines without dielectric liner (non-capsulated) fail early by voiding in the EM tests due to oxidation and deterioration of interfacial adhesion at Cu interfaces. Also at high temperature regimes, extrusive failures under thermal compressive stresses were observed in airgapped Cu lines without dielectric liner. Therefore, Cu encapsulation using a conformal dielectric liner of adequate thickness is necessary in order to ensure hermeticity and provide endurance to the thermal and EM induced extrusive stresses. For an airgapped interconnect with a hermetic 5 nm PECVD conformal carbon doped silicon nitride (SiCN) liner deposited at 370 °C, a (jL)crit comparable to that of non-airgapped interconnects (with ultra-low-k dielectric 2.5 inter-layer dielectric) was predicted by the simulations. The process-oriented simulations reveal, however, that the tensile stress in Cu lines increases linearly with the thickness of the SiCN liner. Therefore, increasing the thickness of the dielectric liner beyond the minimum thickness required for hermeticity was found to impact the critical line length (jL)crit adversely.

Low capacitance and highly reliable blind through-silicon-vias (TSVs) with vacuum-assisted spin coating of polyimide dielectric liners

Low-k and high aspect ratio blind through-silicon-vias (TSVs) to be applied in “via-last/backside via” 3-D integration paradigm were fabricated with polyimide dielectric liners formed by vacuum-assisted spin coating technique. MIS trench capacitors with diameter of ~6 μm and depth of ~54 μm were successfully fabricated with polyimide insulator step coverage better than 30%. C-V characteristics and leakage current properties of the MIS trench capacitor were evaluated under thermal treatment. Experimental results show that, the minimum capacitance density is around 4.82 nF/cm2, and the leakage current density after 30 cycles of thermal chock tests becomes stable and it is around 30 nA/cm2 under bias voltage of 20 V. It also shows that, the polyimide dielectric liner is with an excellent capability in constraining copper ion diffusion and mobile charges even under test temperature as high as 125°C. Finite element analysis results show that TSVs with polyimide dielectric liner are with lower risks in SiO2 interlayer dielectric (ILD) fracture and interfacial delamination along dielectric-silicon interface, thus, higher thermo-mechanical reliability can be expected.

Effect of Design Parameters on Thermomechanical Stress in Silicon of Through-Silicon Via

We examined the effect of the design parameters of a through-silicon via (TSV) on the thermomechanical stress distribution at the bottom of the TSV using finite element analysis. Static analyses were carried out at 350 °C to simulate the maximum thermomechanical stress during postplating annealing. The thermomechanical stress is concentrated in the lower region of a TSV, and the maximum stress in silicon occurs at the bottom of the TSV. The TSV diameter and dielectric liner thickness were two important determinants of the maximum stress in the silicon. The maximum stress decreased with decreasing TSV diameter, whereas the effect of aspect ratio was negligible. A thick dielectric liner is advantageous for lowering the maximum stress in silicon. The minimum dielectric thickness resulting in a maximum stress less than the yield stress of silicon was 520, 230, and 110 nm for via diameters of 20, 10, and 5 μm, respectively. The maximum stress also decreased with the thickness of the copper overburden.

Stress analysis of airgaps under process-induced thermo-mechanical loads

In order to understand the state of process induced stresses in airgap interconnect structures fabricated by the etch-back approach, finite element (FE) models of a 90nm pitch interconnect were developed and a stress analysis of the structure was conducted as a function of the dielectric liner (silicon nitride) and metal barrier (MB) thicknesses. Models of similar structures without airgaps were also developed and the stresses were evaluated as a benchmark case. In addition, a static field solver was used to extract the capacitance of the interconnect structure and evaluate the capacitance reduction by introducing airgaps compared to structures without airgaps. The results identified the sidewall dielectric liner as a critical location where high tensile stress concentration can result in failure of structures under thermo-mechanical loads. Reducing the thickness of the MB and the dielectric liner simultaneously to 1nm and 2nm respectively, minimized metal barrier tensile stresses but increased the tensile stress in the dielectric liner dramatically to 1GPa. Meanwhile, this configuration provided the lowest capacitance and reduced the capacitance of the interconnect by 27% compared to a similar structure without airgaps. In general, reducing the thickness of the MB decreased its stresses both in interconnect structures with and without airgaps.

Real-time diagnostic for charging and damage of dielectrics in accelerators

We report on the progress made during the initial stage of our research to study charging rate and charge distribution in a thin walled dielectric wakefield accelerator (DWA) from a passing charge bunch and the physics of conductivity and discharge phenomena in dielectric materials useful in accelerator applications. The issue is the role played by the beam halo and intense wakefields in charging the dielectric, possibly leading to undesired deflection of charge bunches and degradation of the dielectric material: the effects that may grow over many pulses, albeit perhaps differently at different repetition rates. During the initial stage of development, a microwave apparatus was built and signal processing was developed to observe time-dependent charging of dielectric surfaces and/or plasmas located on or near the inner surface of a thin-wall hollow dielectric tube. Three frequencies were employed to improve the data handling rate and the signal-to-noise. The test and performance results for a plasma test case are presented; in particular, the performance of the test unit shows capability to detect small changes ~0.1% of a dielectric constant, which would correspond to the scraping-off of only 0.3nC to the walls of the dielectric liner inside the cavity from the passing charge bunch.

Dielectric liner reliability in via-middle through silicon vias with 3 Micron diameter

In high aspect ratio through silicon vias (TSV's), the trench step coverage (conformality) of liner, barrier and seed is critical for both the process integration and reliability. If the conformality of a deposition process is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3μm and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctrl) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100°C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS oxide liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD oxide liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications.

Process Development and Optimization for 3 &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu \text{m}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 ${\mu }\text{m}$ top entrant critical dimension and 50 ${\mu }\text{m}$ depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 ${\mu }\text{m}$ TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.