Diameter Wafers Research Articles

Novel and Low-Cost Techniques for Extending the Etch Capabilities of an Inductively Coupled Plasma Etch Tool That Has Clamp Fingers for Clamping 4-Inch Diameter Wafers

Widening the processing capabilities of an inductively coupled plasma (ICP) etch tool by “preventing wafer breakage” during processing of wafers, or by gaining the capability to do “through-wafer silicon etch” are important challenges that may need to be resolved with very limited resources. Resolving the undesired wafer breakage issues caused during processing of wafers is important to reduce the manufacturing costs, and increase production yield. Furthermore, considering the high prices of the state-of-the-art wafer processing tools, it is also important to prevent wafer breakage by using low-cost approaches especially if the resources for purchasing state-of-the-art processing equipment are not available. Two novel methods (method #1, and method #2) are developed to prevent wafer breakage and allow through-wafer silicon etching. With method #1, an aluminium alloy ring (AAR) and an o-ring are employed to obtain uniform load distribution (instead of point loads) on the required outer region on the surface of a wafer, and to minimize or completely remove the bending moment that may be formed on the possible cross-sections of the entire wafer, during clamping of the wafer. With method #2, through-wafer silicon etching is made possible by simultaneous application of method #1 and addition of a helium cooling gas (HCG) leakage blocking dicing tape at the back side of the wafer that is under processing for through-wafer etching. By using the explained methods, wafer breakage during ICP etch processing is eliminated, and through-wafer silicon etching is made possible. From the other side, the effective wafer area that can be used for processing is reduced by 48%. Novel and capability enabling 2 different techniques that are extremely low-cost compared to purchasing a state-of-the-art ICP etch tool are presented to extend the processing capabilities of an ICP etch tool for deep silicon etching (method #1), and through-wafer silicon etching (method #2).

A wireless-feeding capacitive electrode mechanism for achieving massive nanosecond parallel-discharge EDM for large-size wafer flattening

The single-crystal silicon carbide (SiC) wafer diameter is increasing beyond 8 in posing significant challenges to conventional mechanical wafer-processing methods. This study presents an innovative capacitive electrode method for electrical discharge flattening (EDF) of as-sliced large 4H-SiC wafers. The capacitive electrode can be divided into near-infinite units, which significantly reduces the working gap capacitance and enables the generation of a mass of parallel discharges with a nanosecond pulse duration (< 200 ns). This approach offers significant advantages in achieving high efficiency and surface finish simultaneously, regardless of the increase in wafer size. This novel electrode design allows wireless electricity feeding via electrostatic induction, which significantly facilitates the integration of parallel electrode units. Furthermore, a sinusoidal voltage is demonstrated for the first time to identify and promote a parallel discharge state. A model was devised to quantitatively describe the overall process. Using this model, the relationship between the gap voltage, discharge energy, and capacitive electrode properties was predicted, revealing a parallel discharge mechanism. The capacitive electrode mechanism was validated via EDF experiments on a 4H-SiC wafer. Notably, >33 parallel discharges within 6 μs were achieved in a single pulse, resulting in a minimum discharge energy of 0.312 μJ (peak current: 0.18 A, duration: 160 ns) and a surface roughness of Ra 42 nm. Moreover, a machining speed of 0.5 μm/min was achieved on a 4 in wafer, representing an improvement of an order of magnitude compared to conventional non-parallel discharge methods.

Single step silicon carbide heteroepitaxy on a silicon wafer at reduced temperature

A single step growth approach for wafer-scale homogeneous cubic silicon carbide (3C-SiC) heteroepitaxy, using chemical vapour deposition (CVD), on a silicon (Si) substrate is demonstrated. Residual biaxial tensile strain causing a wafer bow is eliminated in the 3C-SiC epilayer via in-situ defects engineering and heteroepitaxy at reduced temperature. Thermal mismatch between the 3C-SiC epilayer and substrate is minimised by a substantial reduction of growth temperature, down to ∼1000 °C. Heteroepitaxy of high quality, fully relaxed 3C-SiC epilayers with minimal wafer bow is demonstrated, made possible by careful process optimisation. Unusually very high growth rate of 3C-SiC of > 10 µm/hr is achieved. At the same time the epilayer is free from any other silicon carbide (SiC) polytype inclusions. Moreover, the reduced growth temperature unlocks the ability to deposit high quality 3C-SiC epilayers within traditional Si-based cold walled CVD reactors, enabling the growth of such thin films on unprecedently high volumes and wafer diameters up to 300 mm and above.

Nanosecond Laser Irradiation for Interface Bonding Characterization

Hydrophilic direct bonding is nowadays widely used in microelectronics for SOI substrate fabrication and 3D integration. Trapped water at the bonding interface plays a key role in the adhesion and adherence mechanisms [1]. Previous studies also reported that water could penetrate the bonding interface. This may modify the radial inhomogeneity of water [2]. However, this reported technique requires specific Silicon-to-Silicon bonding, lacks precision and needs additional characterizations (XRR, FTIR) to quantify the amount of trapped water at the bonding interface. In this work, we present an original methodology that can both accurately characterize and quantify water imbibition.Pulsed nanosecond laser annealing enables to reach extremely high temperatures, above the silicon melting point (1414°C), for very short durations (from a few tens of ns to a few hundred ns). These annealing conditions result in silicon surface melt. The beginning of melting is heterogeneous and leads to a particular surface topology with the formation of molten islands during laser annealing [3]. Recrystallization of these molten islands results in a localized increase of roughness (see fig. 1a). This roughness can exceed the direct bonding critical roughness. Non-bonded areas, i.e. bonding defects, can then be intentionally and precisely placed at the direct bonding interface.In a first step, bonding defects were thus formed along a wafer diameter with a 2 mm pitch. Then, using high-resolution acoustic microscopy, the bonding defects radii evolution was measured over time after direct bonding and without annealing (see fig. 1b). A progressive growth of defect radii was evidenced when getting closer and closer to the wafer edge. An additional water amount coming from the clean room atmosphere resulted in silicon oxidation at room temperature and di-hydrogen generation. Di-hydrogen was then trapped by bonding defects. In other words, bonding defects acted as humidity sensors. We could then record the penetration length and plot it as a function of the square root of time (fig. 1c). The penetration rate is the equivalent of a diffusion coefficient that could be calculated for both Silicon-to-Silicon and Silicon-to-Oxide bonding. We noted a very good agreement with Tedjini’s results for Silicon-to-Silicon bonding [2]. Meanwhile the calculated diffusion coefficient for Silicon-to-Oxide bonding was surprisingly about twice higher.Second, a bonding defect network with the same 2 mm pitch in both X and Y direction was created. After direct bonding, various duration 500°C temperature anneals were performed. The defects radii evolution was once again measured. As it increased over time, we could write the Griffith equilibrium between elastic (due to defect pressure) and surface (γ) energies. Describing defects as circular blisters, the amount of di-hydrogen trapped molecules could then be calculated. Plotting this number of H2 molecules, N, as a function of the annealing time (fig. 1d), we observe that a plateau was reached, meaning that all the di-hydrogen produced in the network was collected in the bonding defects. The water amount responsible for this di-hydrogen generation could then be evaluated and compared to data from other measurements. REFERENCES [1] F. Fournel, C. Martin-Cocher, D. Radisson, V. Larrey, E. Beche, C. Morales, P. A. Delean, F. Rieutord, and H. Moriceau, “Water Stress Corrosion in Bonded Structures”, ECS Journal of Solid State Science and Technology, 4 (5) P124-P130 (2015)[2] Tedjini M, Fournel F, Moriceau H, Larrey V, Landru D, Kononchuk O, et al. Interface water diffusion in silicon direct bonding. Appl Phys Lett. 12 sept 2016;109(11):111603.[3] L. Dagault, S. Kerdilès, P. Acosta Alba, J.-M. Hartmann, J.-P. Barnes, P. Gergaud, E. Scheid, and F. Cristiano, Investigation of Recrystallization and Stress Relaxation in Nanosecond Laser Annealed Si1−xGex/Si Epilayers, Appl. Surf. Sci. 527, 146752 (2020). Figure 1

(Invited) Growth and Characterization of 200 mm SiC Crystals and Substrates

SiC power device technology has over the past years continued to gain massive interest in automotive and industrial applications. The majority of devices is today fabricated on 150 mm diameter substrates while the 200 mm diameter substrates still is at early stage in both development and in terms of mass production. An increase of 50 mm in the wafer diameter corresponds to a 78% larger area and then a corresponding increase of the number of devices per wafer. This change impacts on the productivity of a production line and therefore the cost of the final device can be reduced. Higher production volume and lower cost will lead to a further massive implementation of SiC based power devices in the automotive industry that today is rushing on the path of electrification.At STMicroelectronics we are an early adopter of 200 mm substrates since the first substrate was demonstrated in 2021. Development of 200 mm device quality substrates have progressed well and defect density are today in same range as for 150 mm substrates. The ramp up of production is now made in the new STMicroelectronics plant in Catania while R&D unit in Norrköping Sweden continue to further push the limits of the technology.In this paper, we report the latest progress on STMicroelectronics 200 mm diameter crystals and substrates. We will discuss the most suitable characterization routes available and how we can detect device affecting defects at an early stage. In particular we will start by describing the mechanism that is behind the crystal growth process together with the characterization methods that allow to control the quality of the ingot by monitoring the relevant properties (i.e. bulk defectivity, polytype composition, internal stress). We will then describe the main key parameters to be controlled on the substrate to be sure it is suitable for device making (i.e. mechanical behavior, resistivity, surface roughness, effectiveness of the surface preparation). We will also describe the CVD process that is used to grow on top of the substrate an epitaxial layer with proper resistivity and thickness tailored on the device we need to produce for specific applications. In conclusion we will show some data about the correspondence in between device failure and defectivity on both substrate and epitaxial layer. A comparison of the results collected on both 6” and 8” substrates will be reported to show the excellent job performed in our R&D department in Norrköping to increase the wafer size maintaining the same level of quality. On the other side, our production line in Catania is going to be the first of this kind in Europe with a vertical integration that guarantee process control from the SiC powder to the design and characterization of the final power device.

(Invited) Die to Wafer Direct Bonding: Overview of Processes for Optoelectronic and 3D at CEA

Direct wafer bonding of wafers is nowadays well established. However, direct bonding of dies to wafers can result in innovative devices for optoelectronic or 3D applications (Memory, High Performance Computing...). The paper will focus on specific fundamental mechanisms involved in direct bonding, III/V die-to-wafer bonding and copper hybrid bonding. Die-To-Wafer (DTW) direct hybrid bonding, using copper/oxide mixed interfaces [1] is foreseen by major microelectronics companies as essential for future memory or HPC stacks and as a support to extend Moore’s Law. It indeed increases functionalities per surface unit by optimizing space in three directions: different dies embedding specific technologies coming from different wafers can closely be assembled in one place[2] [3]. However, there are specific integration challenges such as keeping delicate surfaces clean from any degradation or particle contamination after dicing and during die handling and stacking. We describe here important progresses concerning dies preparation as well as alignment with a SET NEO HB die bonder. DTW bonding with 5µm interconnection pitch was demonstrated by CEA with an alignment of 1µm[4]. The capillary approach used during die self-alignment on wafer will notably be discussed [5]. Integrated transmitters incorporating lasers and modulators on silicon are of prime importance for communications. They are at the same time most challenging to manufacture due to a need for hybrid III-V integration [6]. In order to use III-V materials in low cost silicon platforms, direct bonding is of great interest due to difficulties encountered when growing III-V hetero-epitaxial layers directly onto silicon (presence then of anti-phase boundaries, dislocations and so on). Photonic demonstration devices are often processed using as a template a III-V stack on a III-V wafer that is transferred thanks to direct bonding onto a silicon wafer [7]. The potential low cost model of silicon photonics is however based on making full use of the surface of a 200 or 300 mm diameter SOI photonic wafer. III-V wafer direct bonding is thus not suitable for two reasons. First, the maximum diameter available for III-V wafers is up to now limited to 150 mm, while Si-based wafers are nowadays typically 300 mm in diameter. Second, the III-V stack is needed only in the emitter and receiver areas that cover only a very small fraction of the overall device area. Therefore, most of the blanket III-V stack is wasted when removing, thanks to patterning, materials in unwanted area. To overcome this wafer diameter mismatch and limit the loss of a very expensive starting material, a collective die direct bonding seems therefore well adapted. The idea is to collectively bond III-V chips only where there are needed and over the full photonic SOI surface. Until now, only a few teams focused on such an approach. Collective die bonding with an adhesive carrier wafer has however already been demonstrated [8]. At CEA, after exploring a bonding process based on a silicon die wafer holder [9], we describe here an alternative solution using a tape on a dicing frame (see figure 1). As before, throughput is favoured over die placement accuracy. This is well adapted as the transferred layer can be resized by photolithography and etching after the die substrate removal. Furthermore, this approach with a “flexible” tape presents the great advantage of being extremely tolerant regarding die thicknesses variations and enables the use of multiple die wafer sources. We will describe such DTW bonding processes with InP materials. 3 x 3 mm² dies will be used as standard die size for bonding performance evaluation.[1]L. Sanchez et al, ECTC, pp.1960-1964[2] A. Bond et al, ECTC 2022, pp.168-176[3] A. Jouve et al, ECTC 2021, pp.225-234[4] E. Bourjot et al, ECTC 2021, pp 470-475[5]J. Berthier et al, Journal of Applied Physics, 2010, 108, 054905[6] B. Szelag et al, IEEE Journal of Selected Topics in Quantum Electronics, 2019, 25, 8201210[7] J. Durel at al, IEEE IEDM 2016[8] L. Xianshu et al, Journal of Selected Topics in Quantum Electronics, 2016, 22, 8200612[9] L. Sanchez, ECS transactions, 2018, 86, 223-231 Figure 1

(Invited) Wide Bandgap Semiconductor Based Devices for Digital and Industrial Applications

Wide bandgap (WBG) semiconductor devices based on SiC, GaN and Ga2O3 provide advantages for many strategic initiatives in various industrial sectors, such as data centers, electric vehicles, renewable energy systems like solar and wind power inverters. Innovations in WBG technologies would enable new paths on energy efficiency for pushing towards sustainable perspectives. For instance, higher efficiency and lower power dissipation are always desirable for digital economy/society and power electronic applications owing to the energy saving at the end with the goal to reduce CO2 emissions.Here we will emphasize our ongoing WBG semiconductor related research/development and innovation activities, especially on GaN technology owing its rapid/huge demanding in the market nowadays. Thus, the GaN material growth, device processing/packaging and characterization/verification will be elaborated in detail in this talk.In recent years an epitaxy technique to grow large diameter GaN-on-Si wafers by coalesced nanowire has been established at RISE ProNano Lab. The GaN nanowires are epitaxially grown and then merged into a planar epitaxial film with reduced dislocation density as compared to commercially available substrates. It allows for fabrication of thick GaN layers that required for high-voltage vertical devices on Si. A 4.1-µm-thick GaN device layer on a GaN-on-Si template has been grown successfully. It has a threading dislocation density on the order 108 cm-2 and a root mean square roughness of < 0.4 nm. This result has laid the foundation for scaling to the thicker (10-12 µm) crack-free GaN drift layer on lager wafer diameters up to 200 mm.RISE has long term experience working on GaN based High Electron Mobility Transistors (HEMTs). Since 2019 we have worked on high performance and cost-competitive power HEMTs on buffer-free GaN-on-SiC wafers in frame of EU UltimateGaN project. It has focused not only on verification of the high device performance but also on its yield for revealing its competitiveness in the cost-sensitive power electronics market. The fabricated HEMTs demonstrated the expected threshold voltage, good linearity with gate length and width, Ion/Ioff ratio of 1010 as well as high output current up to 16 A with multiple fingers. In such wafer level device fabrication, different types of multi-finger HEMTs could be included with designed electrodes for flip-chip soldering them into package modules. The power module was designed and produced in house by ceramic additive manufacturing (AM), also known as three-dimensional (3D) printing. The package design has aimed to address the stringent thermal and electrical requirements of these types of HEMTs for power electronic applications. Importantly the ceramic AM package design also enables the incorporation of intricate 3D features into the package structure for achieving increased electrical isolation distance between the source and drain contact pads of the HEMT in the package.In addition, SiC and Ga2O3 based sensors/devices will be briefed in this talk, which will provide a glance for design and fabrication of the hybrid WBG components for various greener applications.

Impact-Ionization Switching of High-Voltage Thyristors Connected in Parallel

Thyristors triggered in the impact-ionization wave mode is a promising switching method in pulsed power technology. This triggering approach enhances the current capability of standard thyristors, allowing switching a current pulse with an amplitude of 200 kA and a current rise time rate-of-change (dI/dt) of 58 kA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> s. Thyristor wafer area can be considered as one of the factors that are limiting the peak current amplitude and dI/dt. Switching thyristors in parallel is a possible solution to overcome these limitations. However, no evidence was found in the literature for successful parallel switching of standard thyristors in the impact-ionization wave mode. In this research, the possibility of parallel switching of two standard thyristors rated for 2.2 kV with a wafer diameter of 32 mm was investigated. A Marx generator equipped with a peaking module was used to charge the thyristor equivalent capacitance (1 nF) up to double its static breakdown voltage with a voltage rise time rate-of-change (dV/dt) of more than 1 kV/ns, as required for impact-ionization triggering. The diagnostic system includes two wideband voltage probes (VPs) with a subnanosecond time response, which allows simultaneous measurement of a voltage drop across each thyristor connected in parallel. Two stages of thyristor operation were investigated: 1) a triggering stage, without energy switching, when a dc bias voltage is applied; and 2) a current flow stage, with energy switching, when an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$RLC$</tex-math> </inline-formula> discharge circuit is connected. In these experiments, thyristors change from blocking to conducting state within 400 ps, switching a current pulse with an amplitude of 11 kA and a dI/dt of 6 kA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> s (circuit limits). The current imbalance between the thyristors was less than 10%. To the best of the authors’ knowledge, it is the first time reported that high-voltage thyristors connected in parallel have been successfully triggered in the impact-ionization wave mode.

Development and analysis of thick GaN drift layers on 200 mm CTE-matched substrate for vertical device processing

This work reports the epitaxial growth of 8.5 µm-thick GaN layers on 200 mm engineered substrates with a polycrystalline AlN core (QST by QROMIS) for CMOS compatible processing of vertical GaN power devices. The epitaxial stack contains a 5 upmum thick drift layers with a Si doping density of 2 × 1016 cm−3 and total threading dislocation density of 4 × 108 cm−2. The thick drift layer requires fine-tuning of the epitaxial growth conditions to keep wafer bow under control and to avoid the formation of surface defects. Diode test structures processed with this epitaxial stack achieved hard breakdown voltages > 750 V, which is shown to be limited by impurity or metal diffusion from the contact metal stack into threading dislocations. Conductive Atomic Force Microscopy (cAFM) reveals some leakage contribution from mixed type dislocations, which have their core structure identified as the double 5/6 atom configuration by scanning transmission electron microscopy images. Modelling of the leakage conduction mechanism with one-dimensional hopping conduction shows good agreement with the experimental data, and the resulting fitting parameters are compared to similar findings on silicon substrates. The outcome of this work is important to understand the possibilities and limitations of vertical GaN devices fabricated on large diameter wafers.

Wafer-bonded deep fluidics in BCB with in-plane coupling for lab-on-a-chip applications

The wafer-scale fabrication of deep channel microfluidics for lab-on-a-chip applications by reactive ion etching and wafer bonding is reported. The microfluidic channels are etched in B-stage bisbenzocyclobutene (BCB) and Cytop with the latter used as a bonding agent. The channels are hermetically sealed between Borofloat glass and Si wafers by wafer bonding. Fluidic coupling is achieved in the plane of the channels via inlets and outlets that are revealed on the end facets of chips after dicing. Process techniques and details are reported for uniform coating and curing of BCB and Cytop, defining the channels with high accuracy using photolithography, dry etching the polymers using a hard mask, and sealing the channels by wafer bonding. Fluidic measurements are carried out at various flow rates and compared with modeling. The low Reynold's numbers of the channels ensure laminar flow conditions. Deep fluidic channels are less difficult to align to fluidic interfaces, they support higher flow rates and are less susceptible to clogging. In-plane fluidic coupling precludes the need to etch holes through the substrate. Our wafer-scale process was applied to 4 in. diameter wafers yielding 195 precision-aligned and hermetically sealed microfluidic chips, but is readily scalable to larger diameter wafers for volume production.

(Electronics and Photonics Division Award) Epitaxy of Group-IV Semiconductors for Nanoelectronics and Optoelectronics

Epitaxy stands for the deposition of a perfectly ordered layer on a monocrystalline substrate, which is typically, for group-IV semiconductors, bulk Si or Silicon-On-Insulator (SOI). If the layer is chemically different from the substrate and lattice parameters are not the same, epitaxy can be of two types. If the atomic columns of the substrate extend into the layer with the same in-plane lattice parameter, the layer will be pseudomorphic. The built-in strain will be compressive if the layer has a larger lattice parameter than that of the substrate or tensile if it is lower. If the layer thickness exceeds the so-called critical thickness for plastic relaxation, it will relax, with the formation of misfit dislocations to accomodate the lattice parameter mimatch.Epitaxy of group-IV semiconductors is key for numerous Si-based nanoelectronics and optoelectronics devices. Although they crystallize in the same diamond structure, C, Si, Ge and Sn bandgaps (5.47, 1.12, 0.66 and -0.41 eV), lattice parameters (3.57, 5.43, 5.66 and 6.49 Å) and fusion temperatures (> 4000°C, 1414°C, 938°C and 232°C) are very different. This can be an advantage (bandgap and mobility engineering in devices) or a difficulty (when growing stacks). Finally, although Si and Ge are miscible in all proportions, solid solubilities of C in Si and Sn in Ge are exceedingly low (less than 10-4 % and 0.8%, respectively). Low growth temperatures and high growth rates will then be mandatory in order to have high quality alloys.In that presentation, I will show how epitaxy can be put to good use in order to boost the properties of devices. Layers or stacks were grown on 200 mm and 300 mm diameter wafers in industrial Reduced-Pressure – Chemical Vapour Deposition tools with temperatures in the 300°C-900°C range and pressures in the 20-100 Torr range, typically. Precursors were mono-methysilane (for C), silane, dichlorosilane or disilane (for Si), germane or digermane (for Ge) and tin tetrachloride (for Sn). Finally, diborane and phosphine were the P-type and N-type dopant precursors, respectively.The electrical properties of p-type Metal Oxyde Semiconductor – Field Effect Transistors (MOSFETs) can be improved by the insertion of a thin pseudomorphic SiGe layer beneath the gate of transistors. The compressive strain in it will boost by a factor of ~2 the hole mobility in pMOSFETs. The use of SiGe:B in the sources and drains regions on each side of such devices will help in minimizing the contact resistivity and increasing the compressive strain in the channel. Ramping-up, at high temperatures, the Ge concentration in microns thick layers grown on Si and capping them with constant composition layers will result in SiGe virtual substrates which are almost fully relaxed (e.g. with a lattice parameter close to that of bulk SiGe), slightly defective (Threading Dislocations Density (TDD) around 105 cm-2) and with surface cross-hatches. Growing thin tensily-strained Si layers on top and transferring them onto oxydized Si will result in strained SOI substrates, with an increase by a factor of two of the electron mobility in n-type MOSFETs built on top. Using low contact resistance tensily-strained SiP sources and drains will further boost nMOSFET performances.Microns-thick Ge layers grown directly on Si thanks to a low temperature/high temperature approach can be used as templates for III-V epitaxy. The surface root mean square roughness will be less than 1 nm and the TDD around 107 cm-2 with some short duration thermal cycling. Ge can also be grown selectively in trenches at the end of Si waveguides and near infra-red photo-detectors processed. Microns-thick SiGe layers (capped with Si) and pure Ge layers (capped with SiGe) can otherwise be used to fabricate mid and long Infra-Red waveguides. Mid-IR supercontinuum light was generated when sending ultrashort light pulses in such waveguides. Finally, germanium can be transformed into a direct bandgap semiconductor thanks to high amounts of tensile strain or some alloying with more than 8% of tin. Optically pumped lasing at room temperature was recently achieved in bonded or pillared micro-disks made of thick, plastically relaxed GeSn 16-17% layers.Finally, the feasability of selectively etching SiGe versus Si can be used to fabricate stacked nanosheet MOSFETs, with superior ION/IOFF tradeoffs for a given footprint. The core structures of such devices are epitaxial Si/SiGe superlattices, with the alternance of typically ten nm thick Si and SiGe layers. SiGe layers are later on selectively etched. The resulting voids are conformally filled with gate dielectrics and metals. We recently succeeded in stacking seven Si nanosheets, with a record nMOSFET saturation current of 2.8mA/µm for a 1V drain voltage. Figure 1

Radiation dosimetry for quality control of silicon wafer using electron beam

Dosimetry studies using electron beams were performed with energies of up to 3 MeV, 2mA with various trolley speeds on the silicon wafer. The silicon wafer came with diameters of 152.4 and 203.2 mm with a thickness of 0.5 mm. The irradiations were performed by utilising the EPS 3000 Cockcroft-Walton type 3.0 MeV, 90 kwatts electron beam (EB) accelerator. Plastic film dosimeter, cellulose triacetate (CTA) was used as a dosimeter with a UV-vis spectrophotometer as the readout system. The dose setting in this investigation was ~100 kGy for 152.4 mm diameter and ~160 kGy for 203.2 mm diameter, which was based on the requirements of the customer. The acceptable dose value was set (± 10%) for better performance of the silicon wafer. It was important to comply with the international standards protocol for dosimeters in radiation processing dosimetry. The results showed that the dose and temperature decreased with increasing the speed. The optimum dose for both diameter of wafers when irradiate at electron beam current of 2 mA and the voltage of 3 MeV is at speed of 0.89 m/min. Based on these studies, it was found that it is important to control the speed of the trolley as it affects the irradiation conditions (e.g., temperature and dose measurements).

Structural characterization of epitaxial γ-Ta2N thin films and AlN/γ-Ta2N heterostructures on SiC substrates

Tantalum nitride (γ-Ta2N) thin films were grown by radiofrequency plasma molecular beam epitaxy (MBE) on 3 in. diameter 6H- or 4H-SiC substrates. Epitaxial characteristics of these MBE grown layers were determined using high resolution x-ray diffraction (HRXRD) and transmission electron microscopy (TEM) measurements. HRXRD, TEM, and XRD reciprocal space map measurements show that γ-Ta2N on SiC grows pseudomorphically and stabilizes to a nearly pure γ-Ta2N phase. Structural properties of these layers are uniform across the 3 in. wafer diameter. Measured a and c lattice parameter values of a 43 nm thick γ-Ta2N film on 6H-SiC are 3.079 and 4.898 Å, respectively, and the film has an in-plane tensile strain of 1.03%. MBE growth of AlN/ γ-Ta2N /SiC heterostructures has also been demonstrated. Measured lattice a and c constants of AlN on γ-Ta2N /SiC are 3.120 and 4.974 Å, respectively. TEM and XRD show that SiC substrate and γ-Ta2N films have parallel epitaxial relation.

Optimization of TaSi&lt;sub&gt;2&lt;/sub&gt; Processing for 500 °C Durable SiC JFET-R Integrated Circuits

Experiments are described towards optimizing tantalum silicide (TaSi2) interconnect metal film sputter-deposition and annealing in a manner compatible with the NASA Glenn two-layer interconnect silicon carbide (SiC) JFET-R IC process flow. Films deposited on 100 mm diameter wafers were investigated over a range of film thickness, sputter deposition, and post-deposition anneal conditions. An optimized process that achieved TaSi2 films free of cracking and morphological defects while nearly halving post-anneal stress was developed and will be used for completing the interconnect fabrication of prototype IC Gen. 12 SiC JFET-R ICs.

Silicon Carbide Power Devices: Progress and Future Outlook

Silicon Carbide (SiC) power devices have become commercialized and are being adopted for many applications after 40 years of effort to produce large diameter wafers and high performance device structures. This paper provides a historical perspective of the key breakthroughs that were needed to make progress towards this goal. The JBS rectifier concept was a critical innovation required to make SiC power Schottky rectifiers viable. The Baliga-Pair or Cascode concept was an intermediate step to realize a practical SiC power switch in the 1990s. An essential unique innovation created in the 1990s was the shielded planar SiC power MOSFET structure that is now commonly used for commercial products. Shielded trench-gate SiC power MOSFETs were also proposed in the 1990s which led to commercial products in the last 5 years. Although achieving a low specific on-resistance in SiC power MOSFETs was essential at the inception of the technology, its penetration into power electronics applications is now driven by performance metrics for high frequency circuits. Device structural enhancements to improve the high frequency figures-of-merit are described that have led to major strides in performance. This includes the JBSFET concept where a JBS diode is integrated into the MOSFET structure to suppress current flow through the body diode; the SG and BG MOSFET structures which reduce the gate-drain charge; and the OCTFET structure where the gate-drain overlap area is reduced. Future developments in SiC power devices include increasing the blocking voltage rating to expand the applications spectrum. In addition, a SiC monolithic bi-directional switch has been demonstrated to allow implementation of matrix converters; and a SiC monolithic reverse blocking switch has been demonstrated to allow deployment of current source inverters.

Measurement of axial stress in high-strength short bolts using ultrasonic attenuation

Based on the scattering attenuation theory of loaded polycrystalline metals, a bolt axial stress measurement method using ultrasonic echo attenuation is proposed for the problem that the conventional time of flight (TOF) method is difficult to measure the stress of high-strength short bolts. Firstly, the attenuation coefficients of body-centred cubic crystalline materials in the Rayleigh scattering range are described, and the mathematical model between the ratio of the peak of the two bottom echoes and the axial stress of the bolt is further derived. Then, the effects of the transducer wafer diameter, mounting eccentricity and bolt thread on the ultrasonic signal were analysed by finite element simulation, to provide a strategy for transducer selection and mounting. In addition, a magnetic ring clamping device was designed to ensure a tight fit between the transducer and the bolt, and to improve the alignment of both. Finally, a bolt axial stress ultrasonic measurement system was built, and a comparison experiment between TOF method and attenuation method was conducted to predict the axial stress of bolts. The experimental results shown that the average percentage measurement error of the attenuation method proposed in this paper is 4.42%–5.76% lower than that of the conventional TOF method, which is more suitable for measuring the axial stress of bolts.

Development of all new structure of Dicing Die Attach Film (DDAF) for Stealth Dicing and Cool Expansion processes

Mobile devices, including smart phones and tablets, are increasing in complexity and require ever greater amounts of memory storage. In the past the challenge of higher memory densities and increase functionality has been met through miniaturization of device features, but as we reach the physical limits of feature size, packaging is being relied on more and more to achieve the necessary higher densities in memory and additional device functionality. Thin dies reduce overall package height, however, to achieve high memory densities in low profile packages the die attach material must have an even, thin bond line thickness. DAF (Die Attach Film) is an excellent solution. LINTEC developed an all new DDAF (Dicing Die Attach Film) with thinner DAF for CE (Cool Expansion) process. Conventional tape has a large area of exposed DAF surface which creates the risk of wafer and / or equipment contamination if DAF flies off during the CE process. We developed an all-new tape structure which is compatible with the SD (Stealth Dicing) and CE processes. The structure consists of DAF, IB (Intermediate Basefilm), and dicing tape. The diameter of the DAF and IB is close to the wafer diameter size to significantly reduce the risk of DAF separation and ejection during CE. We considered IB to improve DAF separation and it was found that a thinner IB layer is a good approach to separate DAF effectively. We can adjust adhesion between the DAF and the IB by changing the material properties of the IB, as an effective means to control die-fly and pick-up.

Impact of thermal oxidation uniformity on 150 mm GaAs- and Ge-substrate VCSELs

Vertical cavity surface emitting laser (VCSEL) devices and arrays are increasingly important in meeting the demands of today’s wireless communication and sensing systems. Understanding the origin of non-uniform wet thermal oxidation across large-area VCSEL wafers is a crucial issue to ensure highly reliable, volume-manufactured oxide-confined VCSEL devices. As VCSEL wafer diameters approach 200 mm, germanium (Ge) is emerging as an alternative substrate solution. To this end, we investigate the uniformity of 940 nm-emitting VCSEL performance across 150 mm diameter GaAs- and Ge-substrates, comparing the oxidation method in each case. Nominally identical epitaxial structures are used to evaluate the strain induced wafer bow for each substrate type with Ge exhibiting a reduction of over 100 μm in the peak-to-valley distortion when compared with GaAs. This wafer bow is found to be the principal cause of centre-to-edge oxidation non-uniformity when utilising a conduction-heated chuck furnace, in comparison to a convection-heated tube furnace. Using on-wafer testing of threshold current, differential resistance, and emission wavelength, device performance is demonstrated for the first time across a 150 mm Ge wafer, and is shown to be comparable to performance on GaAs substrates, when the effects of oxidation uniformity are removed. These results provide evidence that there is a realistic path to manufacturing high yield VCSELs, over wafer diameters approaching those used in Si-photonics, via Ge substrates.

Foundry manufacturing of tight-confinement, dispersion-engineered, ultralow-loss silicon nitride photonic integrated circuits

The foundry development of integrated photonics has revolutionized today’s optical interconnect and datacenters. Over the last decade, we have witnessed the rising of silicon nitride (Si3N4) integrated photonics, which is currently transferring from laboratory research to foundry manufacturing. The development and transition are triggered by the ultimate need for low optical loss offered by Si3N4, which is beyond the reach of silicon and III-V semiconductors. Combined with modest Kerr nonlinearity, tight optical confinement, and dispersion engineering, Si3N4 has today become the leading platform for linear and Kerr nonlinear photonics, and it has enabled chip-scale lasers featuring ultralow noise on par with table-top fiber lasers. However, so far all the reported fabrication processes of tight-confinement, dispersion-engineered Si3N4 photonic integrated circuits (PICs) with optical loss down to few dB/m have only been developed on 4-inch (100 mm diameter) or smaller wafers. Yet, to transfer these processes to established CMOS foundries that typically operate 6-inch or even larger wafers, challenges remain. In this work, we demonstrate the first foundry-standard fabrication process of Si3N4 PICs with only 2.6 dB/m loss, thickness above 800 nm, and near 100% fabrication yield on 6-inch (150 mm diameter) wafers. Such thick and ultralow-loss Si3N4 PIC enables low-threshold generation of soliton frequency combs. Merging with advanced heterogeneous integration, active ultralow-loss Si3N4 integrated photonics could pave an avenue to addressing future demands in our increasingly information-driven society.

Low magnetic damping in an ultrathin CoFeB layer deposited on a 300 mm diameter wafer at cryogenic temperature

We deposited an ultrathin CoFeB(1.1 nm) layer, which functions as a storage layer of MgO-based magnetic tunnel junctions for spin-transfer-torque (STT) magnetoresistive random-access memory (MRAM), on ϕ300 mm wafers at 100 K and investigated its effect on the magnetization dynamics of CoFeB. We observed clear reductions in both the inhomogeneous linewidth and total magnetic damping parameter for the CoFeB layer deposited at 100 K compared to those deposited at 300 K through the improvement in the interfacial quality. The results show that deposition at cryogenic temperatures is an effective manufacturing process for high-quality magnetic thin films with low magnetic damping.