Abstract
The single-crystal silicon carbide (SiC) wafer diameter is increasing beyond 8 in posing significant challenges to conventional mechanical wafer-processing methods. This study presents an innovative capacitive electrode method for electrical discharge flattening (EDF) of as-sliced large 4H-SiC wafers. The capacitive electrode can be divided into near-infinite units, which significantly reduces the working gap capacitance and enables the generation of a mass of parallel discharges with a nanosecond pulse duration (< 200 ns). This approach offers significant advantages in achieving high efficiency and surface finish simultaneously, regardless of the increase in wafer size. This novel electrode design allows wireless electricity feeding via electrostatic induction, which significantly facilitates the integration of parallel electrode units. Furthermore, a sinusoidal voltage is demonstrated for the first time to identify and promote a parallel discharge state. A model was devised to quantitatively describe the overall process. Using this model, the relationship between the gap voltage, discharge energy, and capacitive electrode properties was predicted, revealing a parallel discharge mechanism. The capacitive electrode mechanism was validated via EDF experiments on a 4H-SiC wafer. Notably, >33 parallel discharges within 6 μs were achieved in a single pulse, resulting in a minimum discharge energy of 0.312 μJ (peak current: 0.18 A, duration: 160 ns) and a surface roughness of Ra 42 nm. Moreover, a machining speed of 0.5 μm/min was achieved on a 4 in wafer, representing an improvement of an order of magnitude compared to conventional non-parallel discharge methods.
Published Version
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