(Invited) Die to Wafer Direct Bonding: Overview of Processes for Optoelectronic and 3D at CEA

Abstract

Direct wafer bonding of wafers is nowadays well established. However, direct bonding of dies to wafers can result in innovative devices for optoelectronic or 3D applications (Memory, High Performance Computing...). The paper will focus on specific fundamental mechanisms involved in direct bonding, III/V die-to-wafer bonding and copper hybrid bonding. Die-To-Wafer (DTW) direct hybrid bonding, using copper/oxide mixed interfaces [1] is foreseen by major microelectronics companies as essential for future memory or HPC stacks and as a support to extend Moore’s Law. It indeed increases functionalities per surface unit by optimizing space in three directions: different dies embedding specific technologies coming from different wafers can closely be assembled in one place[2] [3]. However, there are specific integration challenges such as keeping delicate surfaces clean from any degradation or particle contamination after dicing and during die handling and stacking. We describe here important progresses concerning dies preparation as well as alignment with a SET NEO HB die bonder. DTW bonding with 5µm interconnection pitch was demonstrated by CEA with an alignment of 1µm[4]. The capillary approach used during die self-alignment on wafer will notably be discussed [5]. Integrated transmitters incorporating lasers and modulators on silicon are of prime importance for communications. They are at the same time most challenging to manufacture due to a need for hybrid III-V integration [6]. In order to use III-V materials in low cost silicon platforms, direct bonding is of great interest due to difficulties encountered when growing III-V hetero-epitaxial layers directly onto silicon (presence then of anti-phase boundaries, dislocations and so on). Photonic demonstration devices are often processed using as a template a III-V stack on a III-V wafer that is transferred thanks to direct bonding onto a silicon wafer [7]. The potential low cost model of silicon photonics is however based on making full use of the surface of a 200 or 300 mm diameter SOI photonic wafer. III-V wafer direct bonding is thus not suitable for two reasons. First, the maximum diameter available for III-V wafers is up to now limited to 150 mm, while Si-based wafers are nowadays typically 300 mm in diameter. Second, the III-V stack is needed only in the emitter and receiver areas that cover only a very small fraction of the overall device area. Therefore, most of the blanket III-V stack is wasted when removing, thanks to patterning, materials in unwanted area. To overcome this wafer diameter mismatch and limit the loss of a very expensive starting material, a collective die direct bonding seems therefore well adapted. The idea is to collectively bond III-V chips only where there are needed and over the full photonic SOI surface. Until now, only a few teams focused on such an approach. Collective die bonding with an adhesive carrier wafer has however already been demonstrated [8]. At CEA, after exploring a bonding process based on a silicon die wafer holder [9], we describe here an alternative solution using a tape on a dicing frame (see figure 1). As before, throughput is favoured over die placement accuracy. This is well adapted as the transferred layer can be resized by photolithography and etching after the die substrate removal. Furthermore, this approach with a “flexible” tape presents the great advantage of being extremely tolerant regarding die thicknesses variations and enables the use of multiple die wafer sources. We will describe such DTW bonding processes with InP materials. 3 x 3 mm² dies will be used as standard die size for bonding performance evaluation.[1]L. Sanchez et al, ECTC, pp.1960-1964[2] A. Bond et al, ECTC 2022, pp.168-176[3] A. Jouve et al, ECTC 2021, pp.225-234[4] E. Bourjot et al, ECTC 2021, pp 470-475[5]J. Berthier et al, Journal of Applied Physics, 2010, 108, 054905[6] B. Szelag et al, IEEE Journal of Selected Topics in Quantum Electronics, 2019, 25, 8201210[7] J. Durel at al, IEEE IEDM 2016[8] L. Xianshu et al, Journal of Selected Topics in Quantum Electronics, 2016, 22, 8200612[9] L. Sanchez, ECS transactions, 2018, 86, 223-231 Figure 1