Single step silicon carbide heteroepitaxy on a silicon wafer at reduced temperature

Abstract

A single step growth approach for wafer-scale homogeneous cubic silicon carbide (3C-SiC) heteroepitaxy, using chemical vapour deposition (CVD), on a silicon (Si) substrate is demonstrated. Residual biaxial tensile strain causing a wafer bow is eliminated in the 3C-SiC epilayer via in-situ defects engineering and heteroepitaxy at reduced temperature. Thermal mismatch between the 3C-SiC epilayer and substrate is minimised by a substantial reduction of growth temperature, down to ∼1000 °C. Heteroepitaxy of high quality, fully relaxed 3C-SiC epilayers with minimal wafer bow is demonstrated, made possible by careful process optimisation. Unusually very high growth rate of 3C-SiC of > 10 µm/hr is achieved. At the same time the epilayer is free from any other silicon carbide (SiC) polytype inclusions. Moreover, the reduced growth temperature unlocks the ability to deposit high quality 3C-SiC epilayers within traditional Si-based cold walled CVD reactors, enabling the growth of such thin films on unprecedently high volumes and wafer diameters up to 300 mm and above.