CMOS Devices Research Articles

Microwave Annealing Technologies for Variability Reduction of Nanodevices: A Review of Their Impact on FinFETs

The rapid reduction of feature size in CMOS devices causes their variability to increase, thus reducing the circuit yield [1]-[3]. In particular, the static random access memory (SRAM) cell uses the smallest transistor to achieve high-density integration, the effect of which is a lower yield [4]. The reduction of variability is, therefore, becoming the most important concern for CMOS devices. In this article, we review the effectiveness of introducing multigate devices and microwave annealing (MWA) for performance enhancement.

Modeling and Circuit Design of Associative Memories With Spin–Orbit Torque FETs

This article introduces a circuits model for a proposed spin-based device called a spin–orbit torque field-effect transistor (SOTFET) that can operate as a nonvolatile memory and logic device. The SOTFET utilizes an FET structure with a ferromagnetic-multiferroic (MF) gate-stack that enables read/compute and write functions to be isolated. This is achieved by a combination of a ferromagnetic layer that is programmable via spin–orbit torque coupled to an MF layer that also couples into the gate of a traditional FET. Additionally, this device has logic gate-like behavior and can be designed to operate in either AND or OR gate mode. We begin with a physics-based model of this device and derive a SPICE level model that can be integrated into the Cadence toolset. Using such a device we demonstrate MRAM, content addressable memories (CAM), and ternary CAM (TCAM) functionality with 3 to 5 transistors, a significant decrease over the CMOS alternative circuits, showing that such a device can enable low cost and compact associative memories not currently feasible with CMOS devices.

Benchmarking Delay and Energy of Neural Inference Circuits

Neural network circuits and architectures are currently under active research for applications to artificial intelligence and machine learning. Their physical performance metrics (area, time, and energy) are estimated. Various types of neural networks (artificial, cellular, spiking, and oscillator) are implemented with multiple CMOS and beyond-CMOS (spintronic, ferroelectric, and resistive memory) devices. A consistent and transparent methodology is proposed and used to benchmark this comprehensive set of options across several application cases. Promising architecture/device combinations are identified.

Fabrication of IGBTs using 300 mm magnetic Czochralski substrates

Up to now the vast majority of insulated gate bipolar transistors (IGBTs) has been produced on silicon (Si) wafers out of the float-zone (FZ) process. FZ crystals can easily be used for this application, but are only available with a diameter of up to 200 mm. However, the use of wafer substrates with a diameter of 300 mm offers a significant increase in productivity and is therefore the diameter of choice for the high-volume production of CMOS devices. In order to benefit from this advantage also for the manufacturing of IGBTs, material out of the magnetic Czochralski process, which is available in 300 mm, had to be adapted. Key issues include crystal originated particles, dopant segregation along the crystal axis, and the higher concentration of oxygen. In particular, the implementation of the field-stop zone by the implantation of protons will lead to the additional formation of hydrogen-decorated C I O I complexes which can act electrically as donors. However, by an appropriate adjustment of the processing parameters the electrical characteristics of IGBTs on FZ substrates can be well reproduced.

Static Power Side-Channel Analysis—An Investigation of Measurement Factors

The static power consumption of modern CMOS devices has become a substantial concern in the context of the side-channel security of cryptographic hardware. Its continuous growth in nanometer-scaled technologies is not only inconvenient for effective low-power designs but does also create a new target for power analysis adversaries. Additionally, it has to be noted that several of the numerous sources of static power dissipation in CMOS circuits exhibit an exponential dependence on environmental factors which a classical power analysis adversary is in control of. These factors include the operating conditions’ temperature and supply voltage. Furthermore, in the case of clock control, the measurement interval can be adjusted arbitrarily. Our experiments on a 150-nm CMOS ASIC reveal that with respect to the signal-to-noise ratio in static power side-channel analyses, stretching the measurement interval decreases the noise exponentially and even more importantly that raising the working temperature increases the signal exponentially. Control over the supply voltage has a far smaller, but still noticeable, positive impact as well. In summary, a static power analysis adversary can physically force a device to leak more information by controlling its operating environment and furthermore measure these leakages with arbitrary precision by modifying the interval length.

A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation

High peak and average efficiency is an important feature of power amplifiers (PAs) for 5G millimeter-wave communication. This article reviews the challenges of conventional outphasing approaches in CMOS technologies and demonstrates a low-loss outphasing combiner for low loadline impedance. Undesirable characteristics of CMOS devices for outphasing are compensated with neutralization, unilaterization, and stabilization networks for the outphasing PA (OPA). The OPA is realized in 45-nm CMOS silicon on insulator (SOI) and demonstrates 40% 6-dB backoff drain efficiency (DE) while providing 17-dBm peak output power with a peak 50.5% DE. For 64-QAM, a 31.3% average DE and 10.1-dBm average output power are measured. The OPA demonstrates less than 1.5% error vector magnitude (EVM) with 64-QAM waveform using a phase-based lookup table (LUT). With 16-QAM, the bit rate reaches 20 Gb/s with 12% EVM. To the best of our knowledge, this is the highest bit rate for a high-efficiency PA. The adjacent channel leakage ratio (ACLR) is under −25 dBc.

First principles calculations of intrinsic mobilities in tin-based oxide semiconductors SnO, SnO2, and Ta2SnO6

The development of high-performance p-type oxides with high hole mobility and a wide bandgap is critical for the applications of metal oxide semiconductors in vertically integrated CMOS devices [Salahuddin et al., Nat. Electron. 1, 442 (2018)]. Sn2+-based oxides such as SnO and K2Sn2O3 have recently been proposed as high-mobility p-type oxides due to their relatively low effective hole masses, which result from delocalized Sn s-orbital character at the valence band edge. Here, we introduce a promising ternary Sn-O-X compound, Ta2SnO6, which exhibits strong valence band dispersion and a large bandgap. In order to evaluate the performance of this oxide as a p-type semiconductor, we perform first-principles calculations of the phonon-limited room-temperature carrier mobilities in SnO, SnO2, and Ta2SnO6. Electron relaxation time is evaluated, accounting for the scatterings from acoustic deformation potentials and polar optical phonons (POP), within the isotropic and dispersionless approximation. At room temperature, the electron/hole mobilities in a given material (SnO, SnO2, and Ta2SnO6) are found to be limited by POP scattering. SnO2 shows high room-temperature electron mobility of 192 cm2/(V s), while SnO and Ta2SnO6 exhibit impressive hole mobilities, with the upper limit at 60 and 33 cm2/(V s), respectively. We find that carrier effective mass largely accounts for the differences in mobility between these oxides with correspondingly different POP scattering rates. The theoretically predicted intrinsic mobilities of each material will provide the upper limit to the real mobilities for their device applications. Our findings also suggest a necessity of further investigation to identify even higher mobility p-type oxides with smaller hole effective masses.

Technology and Modeling of Nonclassical Transistor Devices

This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

Qunatum-Dot Cellular Automata Technology based Optimized Multiplexers Design

Multiplexer plays a dynamic role in the optimization of a digital circuit (FPGA, ALU and memory circuits etc) implementations. Due to continuous Scaling of CMOS device, has already reached to the minimum transistor size, hence , it is not possible to reduce the transistor dimensions further without scaling issues and functionality affect. QCA is one of the emerging and promising new nanotechnologies and is suitable to replace conventional CMOS technology, and potentially able to solve the physical limitations and challenges of CMOS scaling issues. In this paper, the proposed 2:1 multiplexer structure makes the use of inherent characteristics of QCA cells to act as an efficient multiplexer. The proposed QCA based multiplexer architecture improves 50% of design area, 29% of cell count and 75% of the cost when compared with the earlier designed best multiplexer architectures. Higher order multiplexers 4:1 and 8:1 are also designed using proposed 2:1 multiplexer which improved performance to a greater extent relative to existing efficient multiplexer architectures. The design and simulation of circuits have been performed using software tool QCA Designer Version 2.0.3.

Single-Layer GNR Routing for Minimization of Bending Delay

As feature sizes in semiconductor technique scale down, traditional CMOS devices and interconnects are facing several challenges. Graphene nanribbon (GNR)-based devices and interconnects can be treated to be better alternative in nano-scale designs. In this paper, given a set of nets in a single-layer GNR routing (SGNRR) plane, an efficient routing algorithm can be proposed to maximize the number of the routed nets with minimizing the bending delay in SGNRR. The routing process in our proposed algorithm can be divided into three sequential steps: 1) routability-driven net assignment; 2) iterative diffusion-based transformation for delay reduction; and 3) iterative rip-up-and-reroute (IRUR) for delay reduction. In routability-driven net assignment, based on the transformation of multiple-pin nets and the region extraction of two intersected nets in single-layer routing, some detored nets can be selected and the remaining nets can be first routed inside their available regions. Furthermore, the detored nets can be routed by using single-layer obstacle-aware routing. In iterative diffusion-based transformation for delay reduction, the available empty space in an initial routing result can be further used to transform 120° bends into 60° bends. In IRUR process for delay reduction, the routing order of two adjacent nets may be further exchanged to reduce the bending delay if empty space is available. Compared with the combination of the transformation of multiple-pin nets and Yan's negotiated congestion-based algorithm in SGNRR, the experimental results show that our proposed algorithm can use less CPU time to decrease 11.1% of total bending delay with increasing 1.3% of total wirelength on the given nets with the same 100% routability for six tested examples on the average. Additionally, the experimental results show that our proposed algorithm can use less CPU time to increase 5.5% of routability on the given nets for six denser examples on the average.

A Real-Time Vital-Sign Monitoring in the Physical Domain on a Mixed-Signal Reconfigurable Platform.

This work presents a mixed-signal physical-compu-tation-electronics for monitoring three vital signs; namely heart rate, blood pressure, and blood oxygen saturation; from electrocardiography, arterial blood pressure, and photoplethysmography signals in real-time. The computational circuits are implemented on a reconfigurable and programmable signal-processing platform, namely field-programmable analog array (FPAA). The design leverages the core enabling technology of FPAA, namely floating-gate CMOS devices, and an on-chip low-power microcontroller to achieve energy-efficiency while not compromising accuracy. The custom physical-computation-electronics operating in CMOS subthreshold region, performs low-level (i.e., physiologically-relevant feature extraction) and high-level (i.e., detecting arrhythmia) signal processing in an energy-efficient manner. The on-chip microcontroller is used (1) in the programming mode for controlling the charge storage at the analog-memory elements to introduce patient-dependency into the system and (2) in the run mode to quantify the vital signs. The system has been validated against digital computation results from MATLAB using datasets collected from three healthy subjects and datasets from the MIT/BIH open source database. Based on all recordings in the MIT/BIH database, ECG R-peak detection sensitivity is 94.2%. The processor detects arrhythmia in three MIT/BIH recordings with an average sensitivity of 96.2%. The cardiac processor achieves an average percentage mean error bounded by 3.75%, 6.27%, and 7.3% for R-R duration, systolic blood pressure, and oxygen saturation level calculations; respectively. The power consumption of the ECG, blood-pressure and photo-plethysmography processing circuitry are 126 nW, 251nW and 1.44μW respectively in a 350nm process. Overall, the cardiac processor consumes 1.82μW.

Highly Plasmonic Titanium Nitride by Room-Temperature Sputtering

Titanium nitride (TiN) has recently emerged as an attractive alternative material for plasmonics. However, the typical high-temperature deposition of plasmonic TiN using either sputtering or atomic layer deposition has greatly limited its potential applications and prevented its integration into existing CMOS device architectures. Here, we demonstrate highly plasmonic TiN thin films and nanostructures by a room-temperature, low-power, and bias-free reactive sputtering process. We investigate the optical properties of the TiN films and their dependence on the sputtering conditions and substrate materials. We find that our TiN possesses one of the largest negative values of the real part of the dielectric function as compared to all other plasmonic TiN films reported to date. Two-dimensional periodic arrays of TiN nanodisks are then fabricated, from which we validate that strong plasmonic resonances are supported. Our room-temperature deposition process can allow for fabricating complex plasmonic TiN nanostructures and be integrated into the fabrication of existing CMOS-based photonic devices to enhance their performance and functionalities.

Improvement of the electrical performance of Au/Ti/HfO2/Ge0.9Sn0.1 p-MOS capacitors by using interfacial layers

The impact of different interfacial layers (ILs) on the electrical performances of Au/Ti/HfO2/Ge0.9Sn0.1 metal oxide semiconductor (MOS) capacitors is studied. Parallel angle resolved x-ray photoelectron spectroscopy measurements show that germanium diffuses into the HfO2 layer when no IL is used. This results in an increase in the tin content at the interface and a high interface state density. We demonstrate that the use of an IL prevents germanium and HfO2 intermixing and improves the electrical performance of MOS capacitors. Several ILs are studied such as alumina (Al2O3) and plasma oxidized GeSn (GeSnOx) prior to HfO2 deposition. C–V measurements correlated with simulations made by a customized analytical model indicate an interface state density of 5 × 1011 eV−1 cm−2 for the HfO2/GeSnOx/Ge0.9Sn0.1 gate stack. This result is promising for the integration of high mobility GeSn channels in CMOS devices.

Characterization of Au/As2Se3/MoO3/Ag hybrid devices designed for dual optoelectronic applications

In this work, hybrid devices composed of n−As2Se3/p−MoO3 encapsulated between two Schottky shoulders (Au/n-As2Se3, Ag/MoO3) are prepared and characterized. While the structural analyses proofed the preferred growth of monoclinic MoO3 onto amorphous layers of As2Se3, the spectroscopic ellipsometry analysis revealed the high frequency dielectric constants, the effective mass and the negative pseudodielectric constant values. Electrically, the hybrid device displayed both tunneling and standard diode characteristics. As passive mode devices, the capacitance-voltage characteristics displayed the accumulation-depletion -inversion modes in the device. Furthermore, the conductivity spectral analysis has shown that the current conduction is dominated by the quantum mechanical tunneling and correlated barriers hoping mechanisms. The amplitude of the reflection coefficient and the return loss spectral analyses indicated that the hybrid devices are band stop filters in addition to it is usability as nonlinear optical interfaces, CMOS device and tunneling diodes.

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

As CMOS devices become smaller, process variations-induced uncertainty imposes a large spread in the circuit timing and therefore, it becomes one of the main issues for circuit yield. To analyse/optimise the timing of the circuit under process variation effects, statistical analysis/optimisation techniques are more suitable than the traditional static analysis/optimisation counterparts. Statistical gate sizing is an effective technique that is widely used to guide the timing yield improvement of digital circuits. Gate criticality, defined as the probability that a gate lies on a critical path, forms the basis for many of the existing statistical gate sizing techniques. Here, the authors introduce adjacency criticality to address the drawbacks of the conventional definition of gate criticality. It is defined as the probability of manufacturing a chip in which the gate lies on the critical path due to process variation considering the effect of the gates in its fan-out cone. Furthermore, the authors present the levelised Adjacency Criticality metric which provides a trade-off between the runtime of the criticality metric and accuracy of the Adjacency Criticality metric. In order to show the efficacy of the proposed metric, an adjacency criticality-based statistical gate sizing method is presented for improving timing yield of the circuit.

Package Voltage Regulators: The Answer for Power Management Challenges

Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

Efficient Kernel Template AES Algorithm to Minimize Power Consumption and Maximize Security in Low Power Application

Cryptography involved in offering of secure data by generation of secret key through encryption process. At present, almost every applications require security scheme due to increased threats. Low power applications are limited to power sources where incorporation of attacks leads to certain challenges in terms of reduced throughput, data loss and increased power consumption hence it is necessary to adopt effective security scheme for low power application. Generally, in power circuits advanced encryption standard (AES) is incorporated which is defined as S-box. This substitution box is designed by 2 transformations (i.e) inversing the multiplication part in Galois field directed with modified affine transformation. The limitation of S-Box is more time and power consumption. In this paper, proposed a kernel based AES scheme for improving the performance of low power application. The proposed Kernal approach uses logic gate design with cipher text operation. The Kernel -AES technique is implemented in CMOS devices with 45nm standard cell technology. Results obtained for proposed Kernel-AES approach provides reduced power consumption rate of 28.5A which is comparatively less than conventional AES technique.

Contact Resistance Improvement for Advanced Logic by Integration of Epi, Implant and Anneal Innovations

ABSTRACTAs advanced CMOS scaling with FinFETs continues beyond the 10/7nm nodes, contact resistance (Rc) remains a dominant component affecting device performance. The FinFET Source/Drain (S/D) contact area has become smaller with fin pitch scaling, resulting in drastically increased Rc. To achieve higher drive currents and fully realize the performance gain from FinFET architectural changes, it is critical to continue to reduce contact resistivity (ρc) < 1.0x10-9 Ω.cm2 for both NMOS and PMOS. In this paper, we review the recent trends for ρc reduction for advanced CMOS devices and discuss approaches that have demonstrated reduction in ρc, such as in-situ heavily doped epitaxial films for S/D, advanced ion implantation and laser anneals. The implant techniques include pre-amorphization implants (PAI), dopant boosting implants, cryogenic (-100°C) implants for damage engineering and plasma doping (PLAD) for conformal doping of high aspect ratio (HAR) contacts. With such high levels of doping from epi and implants, advanced laser anneals are key for epitaxial regrowth and formation of metastable alloys for dopant supersaturation or segregation in top layers. Millisecond laser anneal (MSA) improves dopant activation and nanosecond laser anneal (NLA) permits superactivation, and both have become key enablers for ρc reduction. This paper also reviews two alternative contact approaches: dual silicide scheme and wrap-around contact (WAC), as potential pathways to further reduce Rc for advanced CMOS nodes.

Integrating GeSn photodiode on a 200 mm Ge-on-insulator photonics platform with Ge CMOS devices for advanced OEIC operating at 2 μm band.

High-performance GeSn multiple-quantum-well (MQW) photodiode is demonstrated on a 200 mm Ge-on-insulator (GeOI) photonics platform for the first time. Both GeSn MQW active layer stack and Ge layer (top Ge layer of GeOI after bonding) were grown using a single epitaxy step on a standard (001)-oriented Si substrate (donor wafer) using a reduced pressure chemical vapor deposition (RPCVD). Direct wafer bonding and layer transfer technique were then employed to transfer the GeSn MQW device layers and Ge layer to a 200 mm SiO2-terminated Si handle substrate. The surface illuminated GeSn MQW photodiode realized on this platform exhibits an ultra-low leakage current density of 25 mA/cm2 at room temperature and an enhanced photo sensitivity at 2 μm of 30 mA/W as compared to a GeSn MQW photodiode on Si at 2 μm. The underlying GeOI platform enables monolithic integration of a complete suite of photonics devices operating at 2 μm band, including GeOI strip waveguides, grating couplers, micro-ring modulators, Mach-Zehnder interferometer modulators, etc. In addition, Ge CMOS circuits can also be realized on this common platform using a "photonic-first and electronic-last" processing approach. In this work, as prototype demonstration, both Ge p- and n-channel fin field-effect transistors (FinFETs) were realized on GeOI simultaneously with decent static electrical characteristics. Subthreshold swings of 150 and 99 mV/decade at |VD| = 0.1 V and drive currents of 91 and 10.3 μA/μm at |VG-VTH| = 1 V and |VD| = 0.75 V were achieved for p- and n-FinFETs, respectively. This works illustrates the potential of integrating GeSn (as photo detection material) on GeOI platform for Ge-based optoelectronics integrated circuits (OEICs) targeting communication applications at 2 μm band.

Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study

In this letter, a planar integration using the deep trench isolation (DTI) technique is proposed to suppress the inter-well parasites in smart power integrated circuits implemented in 0.35 µm BiCMOS technology. In this technology, all devices share the same epitaxial layer. This can lead to a punch-through between power devices as well as between power and low-voltage CMOS devices. A DTI scheme is used to suppress the effect of the parasitic BJT by using a P+ retardation implant region under the deep trench isolation region. The injection ratio of the parasitic BJT is reduced by a factor between 3 and 8.5. The effect of the trench length and the retardation implant is investigated using SENTAURUS TCAD simulations. It is confirmed, through using TCAD simulations, that the amount of the collected carriers of the sensitive devices changes as a function of the trench length and the presence of the retardation implant.