Abstract
Neural network circuits and architectures are currently under active research for applications to artificial intelligence and machine learning. Their physical performance metrics (area, time, and energy) are estimated. Various types of neural networks (artificial, cellular, spiking, and oscillator) are implemented with multiple CMOS and beyond-CMOS (spintronic, ferroelectric, and resistive memory) devices. A consistent and transparent methodology is proposed and used to benchmark this comprehensive set of options across several application cases. Promising architecture/device combinations are identified.
Highlights
T HE unprecedented progress of traditional Boolean computing over the last five decades has been propelled by the scaling of the transistor according to Moore’s law [1]
NEUROMORPHIC WORKLOADS AND HARDWARE We have considered examples of neuromorphic workloads, including convolutional neural networks (CoNNs), such as LeNet [33], [34], AlexNet [35], a single-stage convolution of a 5 × 5 pixel fragment with 24 filters, a single-stage associative memory of pixel patterns [23], a deep neural networks (DNNs) for recognition of handwritten digits from the MNIST handwritten-digit image database [34] implemented as a multilayer perceptron (MLP) with 784 × 256 × 128 × 10 fully connected neurons in layers, and a DNN for speech recognition from [19]—a four-layer MLP with 390 × 256 × 256 × 29 neurons
In summary, the developed methodology described in this article enables quantifying the effect of devices and NN types on the performance, power, and area of NNs
Summary
T HE unprecedented progress of traditional Boolean computing over the last five decades has been propelled by the scaling of the transistor according to Moore’s law [1]. This has spurred research in neural computing that covers a wide field of research, from neural network algorithms that can be programmed on traditional Boolean hardware, such as CPUs or GPUs, to neural network circuits implemented in specialized hardware—application-specific engines. The former approach currently handles the majority of user needs from the data center to the edge. The operation of neuromorphic chips can span a range of circuit implementations from mostly digital to mostly analog (see reviews [5] and [6])
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