Technology and Modeling of Nonclassical Transistor Devices

George V Angelov,Marin H Hristov,Dimitar N Nikolov

doi:10.1155/2019/4792461

George V Angelov, Marin H Hristov + Show 1 more

Open Access

https://doi.org/10.1155/2019/4792461

Copy DOI

Abstract

This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

Highlights

Introduction e progress of VLSICMOS technology continuously follows Moore’s Law (1965)
The dimensions of the conventional metal-oxide-semiconductor (MOS) transistors, respectively, the channel sizes, are scaling into deep nanoscale under 10 nanometers. e hi-tech industry has been foreseeing these developments with the notable International Technology Roadmap for Semiconductors (ITRS) [1]. is roadmap is crucial for the hi-technologies as it takes 10–15 years of research and development efforts for pioneering a new VLSI technology to commercialize and propagate in the market
Advanced structures allowing more aggressive downscaling compared to classical bulk Si transistors such as ultra-thin-body (UTB) silicon-on-insulator (SOI) single-gate transistors and multiple-gate field-effect transistors (FETs) including the already implemented FinFETs, are developed as extensions to conventional metal-oxide-semiconductor field-effect transistor (MOSFET)

Summary

Scaling and Limitations

E concept of scaling implies that performance is improved by reducing the transistors sizes in the integrated circuits (gate length, L, and gate width, W, and the thickness, tox, of the oxide insulation layer between the gate and the substrate) along with reducing the supply voltage and increasing the impurity doping concentration so that the electric field in the device is kept constant (i.e., “constant field scaling”). Is is a crucial parameter, which has been severely scaled to attain enough drive current and to control short channel effects Another solution is to increase the doping of the channel—it leads, to other disadvantages such as decreased mobility, hindered device performance, etc. Ballistic transport effects occur in sub-100-nm channel devices where carriers do not scatter off of semiconductor lattice ions since the channel length is shorter compared to the average free path of carriers

Technology Evolution

Compact Modeling of Bulk CMOS Transistors

Modeling of Multiple-Gate Transistors

Findings

SET Modeling