Development Of Semiconductor Technology Research Articles

Strategic capacity planning for smart production: Decision modeling under demand uncertainty

Semiconductor manufacturing is a capital-intensive industry that capital utilization rate significantly affect the capacity effectiveness and final profit. Capacity portfolio planning strategy must coordinate capacity expansion and migration decisions in balance for utility maximization for smart production and supply chain effectiveness. Manufacturers have to determine capital investments based on various demand forecasts of products in advance for long lead time in manufacturing process. Rapid development in semiconductor technology makes it difficult for companies to estimate future tool requirement especially for new-generation products planning decisions.This study aims to develop an uncertain multi-objective decision (UMD) strategy framework based on uncertainty theory for capacity expansion and migration problem. The objective of proposed model is to minimize the potential loss of capacity oversupply or shortage under uncertain environment. An empirical study was conducted for validation and the results showed practical viability of the proposed approach. The proposed model performs better than existing approach in minimizing the capacity cost loss of shortage, surplus, and migration. Therefore, the proposed approach can be employed as embedded decision support mechanism for smart production solutions for Industry 4.0.

Graphene and related two-dimensional materials: Structure-property relationships for electronics and optoelectronics

The exfoliation and identification of the two-dimensional (2D) single atomic layer of carbon have opened the opportunity to explore graphene and related 2D materials due to their unique properties. 2D materials are regarded as one of the most exciting solutions for next generation electronics and optoelectronics in the technological evolution of semiconductor technology. In this review, we focus on the core concept of “structure-property relationships” to explain the state-of-the-art of 2D materials and summarize the unique electrical and light-matter interaction properties in 2D materials. Based on this, we discuss and analyze the structural properties of 2D materials, such as defects and dopants, the number of layers, composition, phase, strain, and other structural characteristics, which could significantly alter the properties of 2D materials and hence affect the performance of semiconductor devices. In particular, the building blocks principles and potential electronic and optoelectronic applications based on 2D materials are explained and illustrated. Indeed, 2D materials and related heterostructures offer the promise for challenging the existing technologies and providing the chance to have social impact. More efforts are expected to propel this exciting field forward.

(Electronics and Photonics Division Award Address) Compound Semiconductor Science and Technology: A Retrospective

From the earliest days, there has been interest in GaAs and other compound semiconductors due to higher electron mobility than silicon and suitability for optical applications. It was shown in 1962 that semiconductors such as silicon are not suitable for lasers and compound semiconductors were suggested. In the fall of 1962, several groups demonstrated semiconductor lasers under pulsed conditions at 77 K and double heterostructure (DH) laser diodes were achieved in 1970. Coinciding with major advances in fiber optics technology, this provided an enormous impetus for the development of compound semiconductor technology. Epitaxial crystal growth is a most important part of the technology. Liquid phase epitaxy was initially used but was replaced by vapor-phase and molecular beam epitaxy. MOCVD eventually became the vapor-phase technique of choice. Following a breakthrough in GaN technology in the 1990s, the impact of GaN technology is enormous and GaN-based LEDs are rapidly becoming the lighting technology of choice.

Energy minimization for on-line real-time scheduling with reliability awareness

Proposed closed form formulas to quantify static and dynamic system reliability.Proposed an energy efficient on-line algorithm under reliability constraint.Theoretically analyzed the performance of the proposed algorithm.The proposed algorithms significantly outperform the existing related work. Display Omitted Under current development of semiconductor technology, there is an exponential increase in transistor density on a single processing chip. This aggressive transistor integration significantly boosts the computing performance. However, it also results in a power explosion, which immediately decreases the system reliability. Moreover, some well-known power/energy reduction techniques, i.e. Dynamic Voltage and Frequency Scaling (DVFS), can cause adverse impact on system reliability. How to effectively manage the power/energy consumption, meanwhile keep the system reliability under control, is critical for the design of high performance computing systems. In this paper, we present an online power management approach to minimize the energy consumption for single processor real-time scheduling under reliability constraint. We formally prove that the proposed algorithm can guarantee the system reliability requirement. Our simulation results show that, by exploiting the run-time dynamics, the proposed approach can achieve more energy savings over previous work under reliability constraint.

디지털 제어 기반의 경계점모드 브릿지리스 PFC 컨버터

Generally, in order to implement the CRM(Critical Conduction Mode), the analog controller is used rather than a digital controller because the control is simple and uses less power. However, according to the semiconductor technology development and various user needs, digital control system based on a DSP is on the rise. Therefore, in this paper, the CRM bridgeless PFC converter based on a digital control is proposed. It is necessary to detect the inductor current when it reaches zero and peak value, for calculating the on time and off time by using the current information. However, in this paper, the on-time and off-time are calculated by using the proposed algorithm without any current information. If the switching-times are calculated through the steady-state analysis of the converter, they do not reflect transient status such as starting-up. Therefore, the calculated frequency is out of range, and the transient current is generated. In order to solve these problems, limitation method of the on-time and off-time is used, and the limitation values are varied according to the voltage reference. In addition, in steady state, depending on the switching frequency, the inductance is varied because of the resonance between the inductor and the parasitic capacitance of the switching elements. In order to solve the problem, inductance are measured depending on the switching frequency. The measured inductance are used to calculate the switching time for preventing the transient current. Simulation and experimental results are presented to verify the proposed method.

A study on modeling and simulation of Multiple- Gate MOSFETs

Endless scaling of planar MOSFET over the past four decades has delivered proliferating transistor density and performance to integrated circuits (ICs) at the cost of increase in short channel effects (SCEs). As a result of narrow channel lengths in deeply scaled MOSFETs, off-state leakage current happens to increase the power requirement of device by forcing drain potential to lose its leverage over the electrostatics of channel. Multigate devices (Double Gate FET, FinFET) promise better immunity to SCEs by concealing the issues caused by scaling of planar technology, and also exhibits better scalability with increased level of integration. In this paper, a study on modeling and simulation of multiple-gate MOSFETs is presented. This paper describes the development in semiconductor technology from planar to non-planar devices, benefits of multigate MOSFETs over previous technologies. Effects of varying different parameters (such as Fin thickness, Fin height, use of different gate material etc.) in multigate (specially FinFET) devices is also described. Improvement in device physics models along with technology, and importance of computational physics for efficient modeling of nanoscale devices is presented.

GA Based Selective Harmonic Elimination for Five-Level Inverter Using Cascaded H-bridge Modules

Multilevel inverters (MLI) have been commonly used in industry especially to get quality output voltage in terms of total harmonic distortion (THD). In addition, development in semiconductor technology and advanced modulation techniques make MLI implementation more attractive. Selective Harmonic Elimination (SHE) that can be applied MLI at desired switching frequency offers elimination of harmonics in the output voltage. Also, by using SHE technique with cascaded multilevel inverters, the necessity of using filter in the output can be minimized. In this paper, SHE equations have been solved by using of Genetic Algorithm (GA) Toobox&Matlab and it has been aimed to eliminate desired harmonic orders at fundamental output voltage. Simulation results have clearly demonstrated that GA based SHE techniques can eliminate the demanded harmonic orders.

Organic Single Crystals: An Essential Step to New Physics and Higher Performances of Optoelectronic Devices

Organic Single Crystals: An Essential Step to New Physics and Higher Performances of Optoelectronic Devices

Replacement of High-Purity Copper Target by High-Purity Copper Alloy Target in Very Large Scale Integrated Circuit

With the development of semiconductor technology, the size of complementary metal oxide semiconductor (CMOS) devices has been scaled down to nanoscale dimensions. The technology of copper interconnection is the mainstream technology, so the request of the copper target is more and more rigor. This article analyzes the impact factors on the copper alloy target capability, including oxidation and strength. The aim of this investigation is to set up a bridge between the vendors of copper targets and the foundries of integrated circuit (IC) chip, and the base for the next generation copper targets.

Single Tuned Harmonic Shunt Passive Filter Design for Suppressing Dominant Odd Order Harmonics in order to Improve Energy Efficiency

Power quality refers to the provision of the clean and stable electrical power supplies with least interruptions of current and voltage However, power quality problems arise due to the application of nonlinear loads with end user devices. Electrical installations majorly suffer from adverse effects of harmonic currents and voltages. Though, this problem has been decades long and pattern of investigation for the researchers but due to evolution of semiconductor technology, it has become burning issue with reference to the power system loads. Therefore, it becomes necessary to mitigate these harmonics for the safe operation of electrical appliances. Thus, harmonic passive filters are cost effective and easy to implement. In this work, the mitigation of current harmonics has been accomplished through single tuned Shunt Harmonic Passive Filter (SHPF). Furthermore, the application of six pulse multiplication converter technique ensures the mitigation of dominant 3rd harmonic currents and reduction of succeeding 5th and 7th harmonic currents. Furthermore, shunt operation of single tuned harmonic passive filter enables the current to follow the low impedance path. Consequently, the current harmonic distortion becomes less than 5 % according to allowable IEEE 519 -1992 standards. This reduction in harmonic distortion not only reduces the losses incurred in the system but it also improves the energy efficiency of the electrical Power Distribution System (PDS).

The effect of the channel height on the critical heat flux in a shear-driven liquid film

The fast development in semiconductor technology has led to increasingly higher chip power dissipation and greater non-uniformity of the heat dissipation with the result of localized hot spots, often exceeding 1 kW/cm 2 in heat flux. As was shown in previous works of the authors, thin and very thin liquid films driven by a forced gas/vapor flow (stratified or annular flows), i.e. shear-driven liquid films in a narrow channel are promising candidate for an innovative cooling technique optimizing the tradeoffs between performance and cost. The goal of the present work is to study the effect of the channel height on the critical heat flux (CHF) in a locally heated liquid film driven by the shear stress of gas in a channel.

Trend of Energy Saving in Electronic Devices for Research and Development

In electronic industry, energy saving is one of the performance indicators of competitiveness beside price, speed, bandwidth and reliability. This affects research and development (R&D) activity in mechatronic systems which uses electronic components and electronic systems. A review of trend of electronic devices technology development has been conducted with focus on energy saving. This review includes electronic devices, semiconductor, and nanotechnology. It can be concluded that the trend in electronic devices is mainly dictated by semiconductor technology development. The trend can be concluded as smaller size, lower voltage leading to energy saving, less heat, higher speed, more reliable, and cheaper. In accordance to such technology development, R&D activities in mechatronics especially in Indonesia is being pushed to make proper alignment.Some of such alignment actions are surface mount technology (SMT) for installing surface mount devices components (SMD), design layout and SMD troubleshooting tools as well as human resources training and development.

Forty Years of Adventure with Semiconductor Gas Sensors

This work is to summarise briefly the history of the development of semiconductor gas sensors from the point of view of a researcher working in that field through several decades. Statistical evaluation of publication trends, literature review, device technology and theory of operation are included as well as some recent and earlier results of the author and his colleagues and friends working in the field of semiconductor gas sensors.The rapid development of material science and semiconductor technology had a strong effect on gas sensor technology in the past. This trend may be extrapolated to the future; the “More than Moore” principle will be valid in the semiconductor gas sensor field too.

A compact effective-current model for power performance analysis on state-of-the-art technology development and benchmarking

Advances in semiconductor technology have enabled significant performance improvements over the past several decades. However, at the current pace of the development of semiconductor technology, it is increasingly important to achieve a proper balance between performance improvement and power consumption. In this study, to quantitatively analyze the performance and power consumption of new technologies, a compact effective-current model is proposed and used for power performance analysis (PPA). The PPA is performed by separately varying several device characteristics such as drain-induced barrier lowering (DIBL), mobility, and threshold voltage (VT) to determine which options can provide more benefits and better balance for new technologies. The analysis results indicate that the performance improvement due to DIBL reduction (especially below 20 mV/V) is limited. However, VT engineering has more advantages than DIBL and mobility enhancement, unless threshold voltage scaling induces leakage current degradation. Otherwise, mobility enhancement is the most attractive method. By using the proposed compact effective-current model for PPA, we enabled the effective and quantitative estimation of the benefits in terms of performance and power consumption.

Low Power CMOS Look-Up Tables using PROM

Field Programmable Gate Array (FPGA) based designs are the most popular trend towards semiconductor technology evolution. The important subsystem in a configurable logic block is a Look-Up Table (LUT) in the FPGA chip. If the power reduction techniques are implemented in the LUTs, there would be an overall very less power while implementing the design in FPGAs. This study mainly focuses on designing LUTs using Programmable Read Only Memory (PROM) circuits. To implement these LUTs, half adder, full adder, half subtract and full subtractor circuits are chosen with PROM concept. Both the conventional CMOS and pseudo-nMOS style architectures are built for the LUTs. Pseudo-nMOS based LUTs are offering less area and low power compared with conventional CMOS approach. A pseudo-nMOS based full adder LUT design produce 564.5 μm 2 layout area, which is less compared with 765.5 μm 2 produced by conventional CMOS full adder LUT. A pseudo-nMOS based full subtractor design produce 1.119 μW dynamic power dissipation, which is less compared with 3.905 μW produced by conventional CMOS full subtractor. Also the design cycle time for FPGAs are much less compared with ASICs. Simulation results are verified using Microwind and Digital Schematic (DSCH) Electronic Computer Aided (CAD) design tools with BSIM4 MOSFET model in 60 nm technology. This study conveys that how the Programmable Read Only Memory (PROM) can act as a Look-Up Table (LUT) within a FPGA architecture. Since engineers are designing the circuits with most care with circuit design, layout design, etc., Application Specific Integrated Circuits (ASIC) are the best at providing low power, high speed and low size at the cost of design cycle time. But with the current semiconductor technology growth, even FPGAs are being manufactured with high speed with more versatile functionalities.

A Comparative Study of High Speed CMOS Adders using Microwind and FPGA

In the current semiconductor technology evolution, there is a huge demand in designing a low power, high speed adders with less area. As adders are essential components in the data-path of any computer system, adder modules are needed to be enhanced for better performance. One such efficient adder implementation is the Carry Look-Ahead Adder (CLA) which is designed to overcome the latency introduced by rippling effect of carry bits in a conventional Ripple Carry Adder (RCA). Further, the use of this CLA module in the place of Ripple Carry Adder module inside a Carry Select Adder (CSEA) is proposed for increased speed. Also, a novel implementation of adder, making use of the fact that the sum and carry are compliment of one another, except when all the inputs are same is presented. Simulation results show that a 4-bit carry select adder provides a better performance at the cost of power dissipation as 89.211 μW compared with 38.414 μW by a ripple carry adder with 0.12 μm technology processes. In this study, these high speed adders are implemented with the help of the Digital Schematic (DSCH) software tool, Micro wind layout editor tool and Quartus II synthesis software tool. This Quartus II synthesis tool is used for the implementation of adders on Altera EP2C20F484C7 FPGA device. These kinds of adders are further to be extended to build high-speed multipliers which are most important for the applications like digital signal processors, microprocessors, etc.

Suppressed and enhanced shot noise in one dimensional field-effect transistors

Landauer---Buttiker shot noise formula only considers the impact of Pauli exclusion principle on noise, but not the impact of Coulomb repulsion among carriers. A theory recently derived by the authors is able to include also the impact of Coulomb repulsion, and provides a computational methodology to obtain noise properties on a more complete physical basis. We review recent results from the application of this methodology with the use of in-house developed computational electronics tools. We show that in a one-dimensional FET, electrostatic repulsion among charge carriers in the channel can be responsible for strongly suppressed or enhanced shot noise with respect to the Poissonian Noise, or to the noise level provided by Landauer---Buttiker formula. This is very relevant for device and circuit design, since current semiconductor technology evolution has brought nanoscale FETs very close to the limit of one-dimensional FETs.

Reliability of partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistor under the ionizing radiation environment

With the development of semiconductor technology, the small size silicon-on-insulator metal-oxide-semiconductor field-effect transistor devices start to be applied to the aerospace field, which makes the device in use face dual challenges of the deep space radiation environment and conventional reliability. The small size device reliability test under ionizing radiation environment is conducible to the assessing of the comprehensive reliability of the device. With reference to the national standard GB2689.1-81 constant stress life test and accelerated life test method for the general electric stress, the conventional reliability of the sub-micron type partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor is studied under the ionizing radiation environment. The experiment is divided into three groups marked by A, B and C. For all the experimental devices, the gate oxide tox=12.5 nm, channel length L=0.8 μm and width W=8 μm, and nominal operating voltage V=3.5 V. We carry out the electrical stress test on A group after irradiation with γ -ray dose up to 1×104 Gy (Si) under the bias condition. Before group B is tested, it has been irradiated by the same dose γ -ray and annealed for one week. Group C is not irradiated by γ -ray before the electric stress test. After irradiation we measure the DC characteristics of the devices: the drain current versus gate voltage (IDS-VGS) and the drain current versus drain voltage (IDS-VDS). The hot carrier injection (HCI) experiment is periodically interrupted to measure the DC characteristics of the device. The sensitive parameters of HCI and irradiation are VT, GM and IDlin, and after HCI stress, all parameters are degenerated. Through the contrast test, we qualitatively analyze the influences of the oxide trap charge and interface state on the sensitive parameters. We obtain the curve of the oxide trap charge and interface state versus time, and the influences of the different stages on device parameters. The results show that the combination of the total dose radiation environment and electrical stress causes the sensitive parameters of the device to rapidly degrade, this combination of these two factors gives rise to bigger effect than a single influence factor.

Semiconductor Materials Genome Initiative: silicon-based light emission material

The purpose of the semiconductor Materials Genome Initiative is to discover, develop, and deploy new materials in such a way that the research and development period is reduced to a half of original period, and the cost to a fraction of the present cost, thereby speeding up the advance of clean energy sourse, state security, and human welfare, through the organic integration of experiment, computation and theory. Semiconductors play a key role in developing technologies and industries relating to economy, state security, and human welfare. The implement of the semiconductor materials genome initiative will promote the development of semiconductor science and technology into a new era. In this paper, we present a demo of the semiconductor material genome project through introducing our early work on designing silicon-based light emission materials. We first briefly review the status of development of silicon-compatible light emission and challenges facing it. We then demonstrate the power and value of semiconductor materials genome initiative by presenting our recent work on the inverse design of strongly dipole-allowed direct bandgap two-dimensional Si/Ge superlattices and one-dimensional Si/Ge core/multi-shell nanowires, respectively, from two indirect-gap materials (Si and Ge). We use a combination of genetic algorithms with an atomistic pseudopotential Hamiltonian to search through the astronomic number of variants of Sin/Gem//Sip/Geq stacking sequences. We finally give a short perspective of semiconductor materials genome initiative.

Influence of length parameter on the characteristics of nanoscale titanium oxide memristor

According to the completeness theory of circuit, Chua [Chua L O 1971 IEEE Trans. Circ. Theor. 1971 18 507] put forward the fourth basic circuit element memristor besides resistor, inductor and capacitor in 1971. And memorisistance is defined as the ratio of the flux to the charge passing through it. With the emergence and development of nanoscale semiconductor technology, HP laboratoty successfully fabricated a physical memristor in 2008. The successful fabrication of memristive device caused a stir in the whole electronic field and thus a vast number of researchers were involved in the research, owing to its superior properties, i.e., nanoscale dimension, continuous input and output property, switching characteristics and unique non-volatile memory capacity. With all these extraordinary properties, memristors possess many possibilities for the development of future integrated circuits and analog computer. With the gradually in-depth study of memristor, memristor is being microsized, and its internal structure, motion law among its internal particles and influences resulting from the parameters are further explored. In recent years, the memristor has made significant achievement in the areas of non-volatile solid-state memory, intelligent storage, very-large-scale integrated circuitry, programmable analog circuits, and artificial neural networks. So far, the influence of size parameter on the memristor has been little studied, although the size parameter is one of the key factors in the memristor fabrication technology, which severely restricts the memristor development and its practical application. In the paper, we theoretically analyze the influences of size parameter on two practical memristor models (i.e., the HP memristor and spintronic memristor) in detail based on the Ohm’s law. On this basis, a series of circuit experimental simulation is carried out, and the corresponding memristor characteristic curves are thus obtained. Furthermore, we choose 4 most representative experimental results, and make specific analysis on them. Those results indicate that the optimal length of HP memristor is in a range from 8 nm to 12 nm, while the proper range of spintronic memristor is from 500 nm to 600 nm. The final results can not only contribute to memristor physical implementation and its applications, but also provide theoretical references and reliable experiment basis for the further development of the titanium oxide memristor devices and the relevant research.