A compact effective-current model for power performance analysis on state-of-the-art technology development and benchmarking

Abstract

Advances in semiconductor technology have enabled significant performance improvements over the past several decades. However, at the current pace of the development of semiconductor technology, it is increasingly important to achieve a proper balance between performance improvement and power consumption. In this study, to quantitatively analyze the performance and power consumption of new technologies, a compact effective-current model is proposed and used for power performance analysis (PPA). The PPA is performed by separately varying several device characteristics such as drain-induced barrier lowering (DIBL), mobility, and threshold voltage (VT) to determine which options can provide more benefits and better balance for new technologies. The analysis results indicate that the performance improvement due to DIBL reduction (especially below 20 mV/V) is limited. However, VT engineering has more advantages than DIBL and mobility enhancement, unless threshold voltage scaling induces leakage current degradation. Otherwise, mobility enhancement is the most attractive method. By using the proposed compact effective-current model for PPA, we enabled the effective and quantitative estimation of the benefits in terms of performance and power consumption.