Etch Process Development Research Articles

Selective atomic layer etching of HfO2 over silicon by precursor and substrate-dependent selective deposition

The early work of John Coburn and Harold Winters revealed a synergistic effect in ion-enhanced Si etching by the concurrent irradiation of Ar+ and XeF2. This finding provided an important foundation for the development of plasma dry etching processes. The experimental results of Coburn and Winters also found effects that are useful for the development of atomic layer etching (ALE) processes characterized by a self-limited etch rate. ALE approaches are widely established and can be utilized in either directional or isotropic etching by employing proper surface modification and product removal steps. Nevertheless, the development of material selective ALE processes is still limited. An approach that combines substrate-selective deposition with etching opens a new processing window for selective ALE. The authors studied the deposition behavior of mixtures of methane (CH4) with trifluoromethane (CHF3) and mixtures of methane with octafluorocyclobutane (C4F8) on HfO2 and Si surfaces. The experimental results show that a CH4/C4F8 mixture produces a comparable fluorocarbon (FC) deposition thickness on both HfO2 and Si during the deposition step. In contrast, a CH4/CHF3 mixture deposits an FC film on Si, whereas it fluorinates the HfO2 surface with negligible FC deposition. Utilizing these behaviors allows for an ALE process based on CH4/CHF3 for selective removal of HfO2 over Si. Surface characterization data that provide mechanistic insights into these processes are also provided and discussed.

The CORE Sequence: A Nanoscale Fluorocarbon-Free Silicon Plasma Etch Process Based on SF6/O2 Cycles with Excellent 3D Profile Control at Room Temperature

This study focuses on the development of a fluorocarbon-free directional silicon etching process, called CORE (Clear, Oxidize, Remove, and Etch) in which a switching sequence of SF6 and O2 is operated at room temperature. This distinguishes it from the old-fashioned room temperature and cryogenic mixed RIE processes as CORE enables a higher selectivity, creates pattern independency of etching profiles and works excellent at room temperature. The CORE process resembles the well-known SF6-based Bosch process, but the usual C4F8 inhibitor is replaced by O2 oxidation with self-limiting characteristics. Therefore the CORE result is similar to Bosch, however has the advantage of preventing the pile-up of fluorocarbon deposits at the topside of deep-etched or nano-sized features. At the same time, process drift is minimized as the reactor wall is staying perfectly clean. The CORE process has shown an excellent performance in high aspect ratio (3D) nanoscale structures with an accurate and controllable etch rate between 1 and 50 nm min−1 (and SiO2-selectivity of ca. 35) using the etch-tool in the RIE-mode. By adding the ICP source (DRIE-mode), a directional etch rate up to 1 μm min−1 (at 50 sccm SF6 flow) and selectivity >200 for SiO2 is possible.

High-rate etching of single oriented AlN films by chlorine-based inductive coupled plasma for vibrational energy harvesters

This paper presents our development of a high-rate etching process for fully (0002)-oriented AlN films by using a chlorine-based inductively coupled plasma (ICP) and Ni thin films as hard masks. The influences of etching characteristics (etching rate, selectivity) on various parameters (etching power, pressure and gases mixture) were systematically investigated. We achieved etching rate of 723 nm/min, the highest value that has been developed for single-oriented AlN. Etching selectivity was optimized and reached ~ 11, in this report. X-ray photoelectron spectroscopy measurements (XPS) offered a deep understanding of the etching processes and revealed the etching mechanism of AlN by chlorine for the first time.

(Invited) PEALD and ALE for Area Selective Deposition

Advanced CMOS scaling relies on novel structure and design, as well as material developments, which leads to challenging integration issues. Innovation in gap filling technologies, area selective deposition (ASD) and etch processes should help in reaching this scaling specification. Criteria for an adequate area selective deposition process are: growth only on specific regions, high throughput compatible with industrial demands and no so-called mushroom profiles into adjacent features. Several approaches are currently being investigated for the development of ASD processes, among which ASD by surface deactivation with the use of self-assembled monolayers (SAM) or block copolymers, processing temperatures promoting inherent selectivity, and spatial ALD or selective ALD based on ABC-type cycles [1-3]. The original approach developed in our group consists in taking benefit from an in situ etching step inserted in a standard ALD cycle [4, 5]: this so-called deposition/etch approach is already being used for Si epitaxy by the incorporation of HCl in the gas phase. In this presentation, a short introduction on challenges and opportunities for ASD in high volume manufacturing will be presented. A brief state of the art of ASD strategies with their inherent pros and cons will be provided, to open up a discussion on different deposition/etch approaches for Area Selective Deposition, as illustrated in the figure 1. This figure highlights the benefits of developing isotropic as well as anisotropic etching for ASD. Indeed, isotropic plasma etching relies mainly on radical (ie chemical) etching, whereas anisotropic etching can be induced by an appropriate Ion etching process or plasma Atomic Layer Etching (ALE) development. The PEALD/ALE strategy entails a precise energy control of ions flowing from the plasma onto the substrate (with an energy range between 0 and 50 eV). Therefore, a specific design must be conceived for PEALD tool, consistent with this issue. In our work, a low power RF biasing waveform has been applied to the substrate holder in the Flexal deposition tool from Oxford Instruments. Benefits and drawbacks of this deposition/etch approach will be discussed in terms of throughput, etching impact (contamination, roughness…) and process drift. Finally, two examples will be given illustrating a versatile route for topographically selective deposition, either on sidewalls, as needed for spacer fabrication, [6] or on top and bottom of trenches only. This second example will be discussed in regards of surface selective deposition of dielectrics on metal. [1] A. J. M. Mackus et al, Chem. Mater. 31 (2019) 2-12 [2] G. N. Parsons, J. Vac. Sci. Technol. A 37 (2019) 020911 [3] R. Chen, H. Kim, P. C. McIntyre, and S. F. Bent, Appl. Phys. Lett. 84 (2004) 4017 [4] R. Vallat et al, J. Vac. Sci. Technol. A 35 (2017) 01B104 [5] R. Vallat et al, J. Vac. Sci. Technol. A 37 (2019) 020918 [6] A. Chaker et al, Appl. Phys. Lett. 114 (2019) Figure 1

Generating Multiscale Gold Nanostructures on Glass without Sidewall Deposits Using Minimal Dry Etching Steps.

The advent of recent technologies in the nanoscience arena requires new and improved methods for the fabrication of multiscale features ( e.g., from micro- to nanometer scales). Specifically, biological applications generally demand the use of transparent substrates to allow for the optical monitoring of processes of interest in cells and other biological materials. Whereas wet etching methods commonly fail to produce essential nanometer scale features, plasma-based dry etching can produce features down to tens of nanometers. However, dry etching methods routinely require extreme conditions and extra steps to obtain features without residual materials such as sidewall deposits (veils). This work presents the development of a gold etching process with gases that are commonly used to etch glass. Our method can etch gold films using reactive ion etching (RIE) at room temperature and mild pressure in a trifluoromethane (CHF3)/oxygen (O2) environment, producing features down to 50 nm. Aspect ratios of 2 are obtainable in one single step and without sidewall veils by controlling the oxygen present during the RIE process. This method generates surfaces completely flat and ready for the deposition of other materials. The gold features that were produced by this method exhibited high conductivity when carbon nanotubes were deposited on top of patterned features (gold nanoelectrodes), hence demonstrating an electrically functional gold after the dry etching process. The production of gold nanofeatures on glass substrates would serve as biocompatible, highly conductive, and chemically stable materials in biological/biomedical applications.

Effective patterning and cleaning of graphene by plasma etching and block copolymer lithography for nanoribbon fabrication

At a sub-20 nm resolution, patterning 2D materials is necessary in a large number of applications to enhance or control the overall material and device properties. In this work, the authors present their results on the fabrication of graphene nanoribbons using a block copolymer thin film as a lithography mask. A special emphasis is given to the development of new plasma etching processes to pattern graphene and to chemically clean the fabricated nanostructures. At the end, clean 10 nm wide graphene nanoribbons are obtained as confirmed by Raman spectroscopy, x-ray photoelectron spectroscopy, atomic force microscopy, and SEM characterizations. Block copolymer lithography and proper plasma etching conditions allow for easier graphene patterning on a large area and low-cost processing.

Development of air-gap etching process by a mask approach for characterization of intralayer and interlayer capacitances

An air-gap structure was implemented in the metal 2 (M2) layer of a copper interconnect by a mask approach. The fabrication of the air-gap was achieved by tuning etching process parameters such as temperature and etchant chemistry. A residue-free copper surface was realized by optimizing the different steps in the air-gap etching process. The M2 intralayer and interlayer capacitances were measured by using the charge-based capacitance measurement (CBCM) technique and compared with the simulation. Results show that, after the air-gap etching process, with the deposition of 150 Å SiCN on the M2 line with a width of 90 nm, a 22% intralayer capacitance drop was found in the M2 and the 16% ring oscillator frequency was improved. An increase in interlayer capacitance was observed, which resulted from the SiCN thickness decrease on the M2 layer and without the use of dielectric planarization after air-gap formation.

Laser-Assisted Wet Etching of Quartz Crystal Resonators

This paper reports on the development of a laser-assisted wet etching process for quartz crystal resonators. The quartz crystals are in contact with hydrofluoric acid on the backside while the laser is irradiating the front side of the crystal. The quartz crystal has a chromium thin film deposited with thicknesses varying from 5 to 20 nm to absorb the energy from the laser during processing. The laser used has a wavelength of 808 nm ±3 nm with a power output of 5 W. By increasing the power density, the etch rate with the laser setup can be adjusted from 3.8 to 278 $\mu \text{m}/\text{hr}$ . This can be done through beam shaping with focusing lenses. Current wet etching processes require quartz crystals to be frequency trimmed after each step with multiple steps required for processing. With the laser assisted wet etching process quartz resonators can have their frequency tuned by varying the etch rate through adjust the laser’s power density. [2017-0193]

In honor of Professor Kiyokatsu Jinno

At the end of July 2016, Professor Kiyokatsu Jinno retired as an editor of Analytical and Bioanalytical Chemistry (ABC). He was one of the six founding editors when the first issue of the journal appeared in January 2002. Kiyokatsu Jinno (Fig. 1) received his BA (1968), MS degree (1970), and PhD (1973) all from Nagoya University in Nagoya, Japan, working with Professor Daido Ishii, a prominent Japanese separation scientist. Professor Jinno’s doctorate degree, however, was in engineering with research in non-destructive elemental analysis using neutron activation analysis. He then spent the next five years as a research scientist in the Integrated Circuit Laboratory at the Toshiba Research and Development Center working on the development of the dry plasma etching process and electron beam lithographic techniques for large-scale integrated circuits, which he described as Ban active and interesting field^ [1]. In 1978 he was invited to become an associate professor in the School of Materials Science at Toyohashi University of Technology (TUT), a new national technical university just opening at the time of his arrival. At TUT he had been expected to work in the area of radiochemistry using an accelerator that was planned to be built on campus. Unfortunately, the accelerator never appeared, and Professor Jinno was left to find a new area of research. Following the advice of his mentor, Professor Ishii, he chose micro-column liquid chromatography (micro-LC) as his area of research. Professor Jinno remained at TUT until his retirement in 2014 as Full Professor and Vice President of the University. Professor Jinno’s decision to move from activation analysis and elemental analysis to the emerging area of LC was monumental, and he soon became an internationally recognized leader in the field of separation science and related sample preparation techniques. His areas of research during his career span the broad scope of separation science including retention mechanisms and molecular recognition in LC, design of novel stationary phases, development of capillary separation techniques, miniaturized sample preparation techniques and their combination with liquid-phase separations, hyphenated techniques in chromatography and spectroscopy, and the use of computers in separation sciences. He has contributed to a wide range of separation techniques, beyond his primary focus in LC, including micro-LC, capillary electrophoresis, supercritical fluid chromatography (SFC) and extraction (SFE), electrochromatography, gas chromatography, gel permeation chromatography, high-performance thin-layer chromatography, chiral chromatography, solid-phase extraction (SPE), and solid-phase microextraction (SPME). Professor Jinno has been a prolific author with over 310 original research papers, 35 review articles, 39 book chapters, and four books (as author and editor). The exceptional number of review articles, book chapters, and books illustrates the broad range of his contributions. He has presented over 90 plenary and invited lectures at international symposia on chromatography and analytical chemistry. In 2001 a book titled A Century of Separation Science was published highlighting the careers and experiences of many of the founding leaders in the field of separation science. In Professor Jinno’s contribution, BMy Life in Separation Science: Study of Separation Mechanisms^ [1], he states that Bhis contribution to the development of separation science can be divided into at least two main categories: hyphenated * Stephen A. Wise stephen.wise@nih.gov

Silicon nanostructures with very large negatively tapered profile by inductively coupled plasma-RIE

Dry etching of silicon has been extensively studied, mostly with a goal of obtaining perfectly vertical sidewalls with high aspect ratio. Yet, sloped sidewall with a negative taper angle (i.e., diameter/width decreases linearly with depth) may find various applications. However, the systematic study on the etching process development to obtain such a profile is rather scarce. In this work, the authors present a controlled and reproducible fabrication process to achieve silicon nanostructures with negatively tapered sidewall profile using inductively coupled plasma-reactive ion etching with C4F8 and SF6 gas. The plasma etching parameters have been thoroughly optimized in order to avoid the undercut or curved reentrant profile due to isotropic etching, so as to achieve a negatively tapered profile. The influence of the plasma etching parameters, especially the radio freguency power and C4F8/SF6 gas flow ratio, on the etching rate and the sidewall taper angle has been analyzed. With an optimal etching recipe, the silicon nanostructures with an unprecedented large 10° negative taper angle were achieved. These results were demonstrated on different structure sizes of 500 nm, 700 nm, and 1.2 μm diameters.

Characterizing fluorocarbon assisted atomic layer etching of Si using cyclic Ar/C4F8 and Ar/CHF3 plasma.

With the increasing interest in establishing directional etching methods capable of atomic scale resolution for fabricating highly scaled electronic devices, the need for development and characterization of atomic layer etching processes, or generally etch processes with atomic layer precision, is growing. In this work, a flux-controlled cyclic plasma process is used for etching of SiO2 and Si at the Angstrom-level. This is based on steady-state Ar plasma, with periodic, precise injection of a fluorocarbon (FC) precursor (C4F8 and CHF3) and synchronized, plasma-based Ar+ ion bombardment [D. Metzler et al., J. Vac. Sci. Technol., A 32, 020603 (2014) and D. Metzler et al., J. Vac. Sci. Technol., A 34, 01B101 (2016)]. For low energy Ar+ ion bombardment conditions, physical sputter rates are minimized, whereas material can be etched when FC reactants are present at the surface. This cyclic approach offers a large parameter space for process optimization. Etch depth per cycle, removal rates, and self-limitation of removal, along with material dependence of these aspects, were examined as a function of FC surface coverage, ion energy, and etch step length using in situ real time ellipsometry. The deposited FC thickness per cycle is found to have a strong impact on etch depth per cycle of SiO2 and Si but is limited with regard to control over material etching selectivity. Ion energy over the 20-30 eV range strongly impacts material selectivity. The choice of precursor can have a significant impact on the surface chemistry and chemically enhanced etching. CHF3 has a lower FC deposition yield for both SiO2 and Si and also exhibits a strong substrate dependence of FC deposition yield, in contrast to C4F8. The thickness of deposited FC layers using CHF3 is found to be greater for Si than for SiO2. X-ray photoelectron spectroscopy was used to study surface chemistry. When thicker FC films of 11 Å are employed, strong changes of FC film chemistry during a cycle are seen whereas the chemical state of the substrate varies much less. On the other hand, for FC film deposition of 5 Å for each cycle, strong substrate surface chemical changes are seen during an etching cycle. The nature of this cyclic etching with periodic deposition of thin FC films differs significantly from conventional etching with steady-state FC layers since surface conditions change strongly throughout each cycle.

Effect of the C-bridge length on the ultraviolet-resistance of oxycarbosilane low-k films

The ultra-violet (UV) and vacuum ultra-violet (VUV) resistance of bridging alkylene groups in organosilica films has been investigated. Similar to the Si-CH3 (methyl) bonds, the Si-CH2-Si (methylene) bonds are not affected by 5.6 eV irradiation. On the other hand, the concentration of the Si-CH2-CH2-Si (ethylene) groups decreases during such UV exposure. More significant difference in alkylene reduction is observed when the films are exposed to VUV (7.2 eV). The ethylene groups are depleted by more than 75% while only about 40% methylene and methyl groups loss is observed. The different sensitivity of bridging groups to VUV light should be taken into account during the development of curing and plasma etch processes of low-k materials based on periodic mesoporous organosilicas and oxycarbosilanes. The experimental results are qualitatively supported by ab-initio quantum-chemical calculations.

Deep SiO2 etching with Al and AlN masks for MEMS devices

Silicon oxide-based materials such as quartz and silica are widely used in microelectromechanical systems (MEMS). One way to enhance the capability of their deep plasma etching is to increase selectivity by the use of hard masks. Although this approach was studied previously, information on the use of hard masks for the etching of silicon-oxide based materials on 200 mm substrates is scarce. We present the results of etching process development for amorphous silicon oxide using Al and AlN masks with a view of the application of the results for the etching of silica and quartz. Three gas chemistries (C4F8/O2, CF4 and SF6) and their mixtures were compared in an industrial reactive ion etch (RIE) chamber with two plasma sources. It was established that pure SF6 is the best etchant and AlN is a better mask than Al for providing higher selectivity and a sidewall angle close to vertical. A range of etching parameters for micromasking-free etching was established and etched structures of up to a 4 : 1 aspect ratio were created in 21 μm-thick oxide using the process with an etch rate of 0.32–0.36 μm min−1 and a selectivity to AlN mask of (38–49) : 1.

Wetting Behavior of Plasma Etch Residue Removal Solutions on Plasma Damaged and Repaired Porous ULK Dielectrics

Porous ultra low constant materials (ULK) for isolation within the interconnect system of integrated circuits are a promising approach to reduce crosstalk and RC-delays due to shrinking feature sizes [1]. Due to their porosity and the integration of carbon rich species like methyl groups into the Si-O-Si backbone of currently fabricated PECVD SiCOH dielectrics those materials are highly sensible towards plasma processing, e.g. dry etching or resist stripping [2]. Metal hard mask approaches, e.g. using TiN hard masks are widely used to prevent the resist stripping plasma directly attacking the low-k material [3]. To reduce further plasma damage like carbon depletion and formation of polar silanol groups the development of less aggressive etching processes is in the focus of research and development activities. Nevertheless dry etching will attack the sidewalls and cause a material degradation. That is why repair processes, mainly based on silylation, are considered to follow the patterning step to reintegrate carbon rich species and to recover the dielectric’s properties [3]. Subsequently to dry etching and repairing the dielectric the wet chemical plasma etch residue removal process is performed. Besides material compatibility and effectiveness in residue removal the wetting behavior of the applied cleaning solutions towards the surface which has to be cleaned is crucial, especially looking on wetting issues like the incomplete wetting of very small via holes or pattern collapse. In this study we investigate in which way different silylation based repair processing regimes are affecting the wettability of the dielectric by water based cleaning solutions using contact angle based surface energy calculations.

Development of plasma etching processes to pattern sub-15 nm features with PS-b-PMMA block copolymer masks: Application to advanced CMOS technology

The best strategies to transfer nanoholes formed from the self-assembly of Polystyren/Polymethylmethacrylate (PS/PMMA) based block copolymers into a silicon substrate are investigated. The authors show that specific issues are associated with the plasma etching of materials through the PS masks obtained from self-assembly. Indeed, due to the nanometric size of sub-15 nm contact holes and to their inherently high aspect ratio (>5), plasma etching processes typically used to etch SiO2 and silicon in the microelectronic industry must be revisited. In particular, processes where the etching anisotropy relies on the formation of passivation layer on the feature's sidewalls are not adapted to nanometric dimensions because these layers tend to fill the holes leading to etch stop issues. At the same time, the ion bombarding energy must be increased as compared to a typical process to overcome differential charging effects in high aspect-ratio nanoholes. However, by developing appropriate processes—such as synchronized pulsed plasmas—the authors show that it is possible to etch 70 nm deep holes into silicon by using block copolymers and a hard mask strategy. Another interesting observation resulting from these experiments is that for sub-15 nm holes, a critical dimension (CD)-dispersion of few nm leads to strong aspect ratio dependent etch rates. In addition, a careful analysis of the dispersion of the holes' CD after each plasma steps shows that the CD control is far from satisfying advanced CMOS technology requirements. A critical issue comes from the uncompleted PMMA removal from the PS/PMMA matrix during our self-assembly process: variable amount of PMMA remains in the PS holes, leading to microloading effects during the etching steps, which in turn generates CD-control loss. This problem perhaps can be solved by combining UV exposure to acetic acid treatment to provide PS masks free of PMMA residues before plasma etching.

Scaling the 3D Bumps Pitch from 20 to 10 μm, Focusing on the Wet Cu Seed Etch Process Development

Within 3D stacked integrated circuits (3D-SIC), the fabrication of well-defined and solid microbumps is required. These bumps are typically being processed in presence of probing metal such as Al in order to stack functioning dies [1]. As a result of the variety of metals present and the continuous microbump downscaling towards 10 μm, more selective Cu seed etch chemistries are being screened. These Cu seed etch chemistries should be compatible with a variety of metals (Ni, Sn, Al, Co) and generate bumps without undercut and acceptable lateral etch (< 300 nm/side for 20 μm and < 150 nm/side for 10 μm). However the lateral etch specifications were just met for 20 μm [2] and will be more stringent for 10 μm, especially as the lateral etch specification are within the same range as the Cu seed layer thickness (150 nm). Additionally, the current seed etch process is yielding rough bumps (Rs >15 nm) whereas our target is set to be <12 nm in order to guarantee a good electrical contact.

Improvement of GaN Deep Etched Surface State by Fluorination Dedicated to Power Devices

Gallium nitride (GaN) is a III-V semiconductor with a large and direct bandgap (3.4 eV). Due to this bandgap, GaN is already used in optoelectronic applications for blue Light Emitting Diodes (LED), white LED and Blu-ray disc. Furthermore, GaN has a high electron mobility and strong chemical bonds (8.92 eV). These physical properties make GaN very interesting for microelectronics and open new prospects. Indeed, GaN-based devices, compared to silicon devices, can operate under high temperature, high power and high frequency. For GaN-based power devices, an etched depth as high as 6 to 10 µm is typically required. This is considered as deep etching compared with the usual etched depth for light emitter devices (a few hundred nanometers) [1]. It was shown that wet etching of GaN c-plan (plan where etching is generally needed) is limited due to its chemical inertness [2]. Therefore, GaN deep etching is achieved by plasma etching. Chlorine-based chemistries are commonly used because GaCl3is the most volatile Ga etching product. GaN (8 µm thick epilayer grown on Si) MESA etching was studied in Cl2/Ar based plasmas using two industrial Inductively Coupled Plasma (ICP) reactors (with and without diffusion chamber) and Ion Beam Etching (IBE). Our studies were carried out on samples mounted on a carrier wafer. After etching, regimes of defects were observed. Etch pits are linked to nanopipes and dislocations created during epitaxial growth of GaN [3]. Preferential oxidation of dislocations leads to columns appearance. Oxygen based species come from either the SiO2 carrier wafer or the alumina/quartz tube of ICP sources. In the case of surface over-oxidation, a very rough surface, called “White GaN”, is obtained. For industrial applications, both defects and roughness must be limited. Using these 3 reactors and different carrier wafer materials, etched GaN surfaces were compared in order to point out the best etching condition. In ICP reactors, usual Cl2/Ar based-chemistry was modified. Addition of SiCl4, CHF3 or SF6 combined with the use of a Si carrier wafer results in a decrease of the defect density and, in some cases, in their elimination. Plasma and surface investigations by Langmuir probe, OES, mass spectrometry, XPS, SEM and AFM were performed to better understand GaN defects formation and Ga/N surface ratio modification. It was observed that fluorine species are able to protect GaN surface with the formation of a GaxFy -like “passivation layer”. This result led to the development of a time-multiplexed etching process consisting in alternating etching and passivation steps. After etching, ripples were clearly visible on the sidewalls. This process appears to be a way to etch GaN without defects even if the carrier wafer is made of SiO2. Defect free GaN etched surface can also be obtained using IBE technique. An optimum angle of 30° between the Ar+ion beam and the GaN surface was find to etch dislocations at the same rate as c-plan.Finally, we studied the selectivity of GaN with different mask materials for IBE and ICP chlorine plasmas. A selectivity as high as 6 using ICP etching with a SiO2 mask was obtained, with a GaN etch rate of 1 µm.min-1. By using IBE, a selectivity of 5 was obtained with a TiN mask.ReferencesP. Waltereit, O. Brandt, A. Trampert, H. T. Grahn, J. Menniger, M. Ramsteiner, M. Reiche and R. H. Ploog, Nature, 406 (2000) 865-868D. A. Stocker, E. F. Schubert and J. M. Redwing. Applied Physics Letters, 73 (1998) 2654-2656J. Ladroue, A. Meritan, M. Boufnichel, P. Lefaucheux, P. Ranson and R. Dussart, J. Vac. Sci. Technol. A, 28 (2010) 1226

Etch Challenges for 3D NAND Flash Technology

Current 2D NAND scaling is approaching technology limitation in both lithography and device performance arena. To address the lithography challenges at the 1x nodes and the well-known scaling issues associated with planar NAND, 3D flash technology is being developed and is expected to greatly reduce the lithography burden albeit shifting it to deposition and etch. The emerging 3D flash architecture requires depositing alternating layer stacks and then etching those stacked layers with extreme precision. Staircase etch for contact landing, hard mask etch, gate trench etch, channel hole etch and staircase contact etch are the main critical etches required to manufacture 3D flash device (Figure 1). Plasma etching processes involved in the fabrication of 3D flash devices are becoming increasingly challenging. The staircase etch, which requires lateral resist mask etch followed by vertical stacked layer etch, repeated in multiple the lateral/vertical etch cycles, to form staircase shaped contact landing pads, offers unique challenges in lateral to vertical etch rate control of resist mask, resist mask shape control, selectivity control of the stacked layer etch, staircase step width control and step width uniformity control. Hardmask open, gate trench etch, channel hole etch, and staircase contact etch create significant challenges for etching, especially of high aspect ratio (HAR) features ranging in aspect ratio from 30:1 to >80:1. Furthermore, etching through the HAR alternating layer stacks intensifies the demands on the etch process, which must be capable of etching distortion free, vertical profiles free of bending, faceting and feature clogging. Additionally, smooth sidewall transitions in the alternating stack, and very high selectivity to the tiny pad are required, especially for the staircase contact etch application, which combines extreme simultaneous multi-level etch at aspect ratios ranging from 30:1 to >80:1 along with extremely high selectivity for negligible loss of the underlying contacted material.In this paper we will present etch hardware and process development solutions provided to overcome these difficult etch challenges for staircase etch, hard mask open, gate trench etch, channel hole etch, and staircase contact etch applications to enable 3D NAND flash technology.

Total Solutions for 40nm Metal Hard-Mask All-In-One Etch Process

MHM (Metal Hard Mask) AIO (All-In-One) etch is one of key BEOL (Back-End-Of-Line) processes for 40/45nm technology node and beyond. In this work, we focus on some key issues and solutions that we encountered during 40nm MHM AIO etch process development in HLMC. Main issues including: TiN thickness optimization, trench profile optimization, kink profile optimization, chamfer profile control, TixFy residue issue, via profile control, trench Bottom roughness issue, via bottom integrity control etc. For above process challenges, the article gives detail analysis and then provides final solutions which can meet all process requirements after balancing and optimizing all process parameters under current hardware’s conditions.

Fluorocarbon assisted atomic layer etching of SiO2 using cyclic Ar/C4F8 plasma

The authors demonstrate atomic layer etching of SiO2 using a steady-state Ar plasma, periodic injection of a defined number of C4F8 molecules, and synchronized plasma-based Ar+ ion bombardment. C4F8 injection enables control of the deposited fluorocarbon (FC) layer thickness in the one to several Ångstrom range and chemical modification of the SiO2 surface. For low energy Ar+ ion bombardment conditions, the physical sputter rate of SiO2 vanishes, whereas SiO2 can be etched when FC reactants are present at the surface. The authors have measured for the first time the temporal variation of the chemically enhanced etch rate of SiO2 for Ar+ ion energies below 30 eV as a function of fluorocarbon surface coverage. This approach enables controlled removal of Ångstrom-thick SiO2 layers. Our results demonstrate that development of atomic layer etching processes even for complex materials is feasible.