SRAM Design Research Articles

Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing

Convolutional neural network (CNN) has been widely deployed in various processors for intelligent visual signal processing. However, the large amount of activations and weights in CNN causes huge power consumption on SRAM access. Data-adaptive SRAM design is a widely studied method to reduce SRAM reading power based on the utilization of data patterns, while current designs only exploit data patterns in a coarse granularity, and have no advantages when faced with randomly distributed weight data. In this article, we propose a hardware–software co-design scheme to reduce SRAM reading power for CNN processing. First, we propose a reconfigurable data-adaptive SRAM architecture with column data segmentation (CDS-RSRAM) to utilize data patterns. Data in one column is partitioned into several segments, and finer-grained data patterns are exploited within each segment for further reading power reduction. Then, a novel training method—minimum segmented neighbor difference (miniSND)—is proposed for enhancing the correlation of weights. MiniSND improves the similarity of weights without classification accuracy degradation, thus weights could benefit from CDS-RSRAM and be read out with less power consumption. Simulation results demonstrate that the co-design scheme saves up to 66%(8b)/89%(2b) power consumption compared with 8T SRAM.

Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design

Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design

2-D Strain FET (2D-SFET) Based SRAMs—Part I: Device-Circuit Interactions

In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to $2.7\times $ larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of 2D-SFET (as drop-in replacement for standard 2D-FET) in 6T-SRAM for a range of design parameters and compare those to 2D-FET 6T-SRAM. 2D-SFET 6T-SRAM achieves up to 5.7% lower access time, 63% higher write margin, and comparable hold margin, but at the cost of comparable to 11% lower read stability and 16% increase in write time. In Part II of this article, we mitigate the read stability issues of 2D-SFET SRAMs by proposing ${V}_{{\mathrm {B}}}$ -enabled SRAM designs.

English

English

Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap

The device scaling restricted due to the limitation of the subthreshold swing of the MOS transistor, which is not less than 60 mV/dec. The researchers are concentrating more on power efficient techniques for advanced, more featured, electronic systems. In place of MOS transistor, which is homojunction, if a heterojunction transistor with low bandgap materials used, the subthreshold swing of the transistor being reduce to below 60 mV/decade and low leakage current can obtain. Ge, GeSi, etc. materials are used in the design and implementation Heterojunction Tunneling Transistor (HETT) due to low band gap.In this work, both types of HETTs such as NHETT and PHETT designed and implemented using low bandgap materials with a technique of increasing tunneling area by overlapping. The performance of NHETT and PHETT described by the design and implementation of 7T MOSFET SRAM. The power and delay analysis of this SRAM cell using HETTs presented, and the results compared with MOSFET based standard 6T, conventional 7T SRAM cells.

A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.

Design of Low Power 6T Sram with and without ROFs

An aggressive scaling in size and the increasing number of the transistor count are the important challenge of the design of Integrated Circuit (IC). In the same manner interconnection lines and resistive opens also became a major problem in present nanometer technology. The resistive open faults [ROFs] represent degradation [1] in connectivity’s within a circuit’s interconnections because of unavoidable manufacturing failures present in both current and future developing technologies. The resistive open fault [ROF] is an imperfect circuit connection that can be modelled as a defect resistors between two nodes of the circuit. The Resistive open faults [2] not causes the functionality of the circuit instantly. But, it causes the delay faults. In this research proposal, the impact of resistive open faults measured in 6-Transistors (6T) Static RAM memory cell design. The proposed 6T Static RAM memory cell implemented in 45nm technology by using Cadence Virtuoso library. The main goal of this proposed research work is to analise the effect of resistive open faults and how it reduce delay and power of 6T Static RAM cell. The resultant outputs of proposed 6T SRAM cell operation with and without ROFs will be compared.

Stability Enhancing SRAM cell for low power LUT Design

Field Programmable Gate Array (FPGA) is the most recently used platform for real time applications such as security and multimedia processing. In FPGA mapping, there is some energy overhead due to the usage of programmable interconnects. To mitigate these limitations an energy efficient six input Look Up Table (LUT) is designed using Stability Enhancing Static Random-Access Memory (SESRAM) cell requiring only seven transistors. The proposed SESRAM cell reduces the area, power consumption, energy consumption, delay and increases the read stability, write stability by minimizing the size of read access transistor as 2 ​nm and maximizing the size of write access transistor as 3 ​nm. The proposed SE7T reduces the write ‘0’ delay and write ’1’ delay by 62.5%, 57.14%, 50%, 40%, 25% and 70%, 62.5%, 57.14%, 50%, 40% respectively at 0.4 ​V when compared with previous SRAM designs such as C6T, D2AP8T, LP8T, ST10T and PFC10T. LUT using SE7T reduces the Write ‘0’ power by 93.4%, 68%, 21.21% and Write ‘1’ power by 2%, 50.16%, 10.13% when compared with LUT design using ST10T, D2AP8T and PFC10T.

High Speed Novel Design of Sram for Highly Reliable Applications

Modern ICs are enormously complicated due to decrease in device size and increase in chip density involving several millions of transistors per chip. The rules for manufactured leads to a tremendous increase in complexity due to the amount of power dissipation are increased. In this paper, the design of novel SRAM is implemented for the highly reliable applications. For high-speed memory applications such as cache, a SRAM is often used. Power consumption is the key parameter for an SRAM memory design (SRAM). New tag generation system designed for integrity checking of SRAM. A single read operation to a crossbar SRAM that can be used for integrity checking. Reliability of the system is measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage.

Design of 8T CNTFET SRAM for Ultra-Low Power Microelectronic Applications

At around 10nm, direct source to drain tunneling in COS-MOS technology constituting fundamental limitations that in turn hold back their suitability for modern electronic appliances chiefly as far as area, energy competency and performance. In advanced electronic appliances, memory constituents play a crucial part. Almost in every digital appliance, memory component is mostly preferred due to its unique potentiality to withhold information. Due to rapid technology advancements, architecture of SRAM is truly tested as far as delay, energy efficiency and stability. Traditional 6T memory unit experiences passage transistor conflict arises the contrast among read balance and write competence. The paper that proposed here contrasts the performance of distinctive CNTFET based 8T memory unit architectures like Traditional and Dual-Port with respect to write delay, read delay and power efficiency like static and dynamic. 8T SRAM bit cell is designed with 32nm CNTFET technology using HSPICE Tool. From the HSPICE simulation results, Dual-Port CNTFET SRAM has provide better read and write delays were reduced by ~8.8% and ~16.3%, static power and dynamic power by ~12.5% and ~42.2% respectively than conventional one.

Energy Efficient SRAM

Memories are an essential unit of any digital circuit, thus their power consumption must be considered during the designing process of the cells. To improve performance, reduce delay and increase stability, it is advisable to decrease the power consumed by the memory. Due to high demand of speed, high performance, there’s a need to decrease the size of the device, thereby increasing the devices placed per chip. This high integration makes chips more complex but improves device performance. Design of SRAM cells with speed and low power is crucial so as to replace DRAMs. The layout of SRAM has advanced to meet the requirements of the present industry in accordance with parameters like delay, power consumption and stability etc. This paper presents the aim of analyzing different technologies used to make SRAM more efficient in terms of parameters such as static noise margin, latency and dissipation of power. The stability investigation of SRAM cells are usually derived from the Static Noise Margin (SNM) analysis. Here we observe a SRAM design which has used dynamic logic and pass transistor logic. We further study the effects made on this design by employing various technologies such as AVL-S, AVL-G, AVL and MT-CMOS, at 180nm CMOS technology to achieve enhancements in delay, power consumption and performance. The proposed circuits are simulated and the results obtained have been analyzed to show significant improvement over conventional SRAM designs. Cadence Virtuoso simulation is used to confirm all the results obtained in this paper for the simulation of 180 nm CMOS technology SRAMs.

Design and Simulation of Novel TG8T SRAM

Design and Simulation of Novel TG8T SRAM

Радиационно-стойкое проектирование высокопроизводительных нанометровых КМОП СБИС «система-на-кристалле»

The influence of the dominant radiation effects in bulk CMOS IC and VLSI on their electrical parameters and characteristics is analyzed. The effects of scaling and electrical modes on device and parasitic n-MOS transistors on the radiation hardness parameters are considered. The methodology of radiation-hardening-by-design of system-on-chip (SoC) and SRAM was developed for the 250-90 nm bulk CMOS processes. Technical solutions are proposed that provide an increased level of total ionizing dose tolerance, failure tolerance, and the absence of the latch-up effect. The framework for high-performance radiation-hardened SoC and SRAM design, containing standard cell libraries and IP-blocks, has been created. Basic technical solutions are certified on special test chips and as part of developed VLSI.

A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach

Near threshold computing (NTC) has significant role in reducing the energy consumption of modern very large scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This paper presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this paper, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture level analysis. Their experimental results show that in NTC, process variation and aging-induced SNM degradation is $2.5{\boldsymbol \times }$ higher than in the super threshold domain while SER is $8{\boldsymbol \times }$ higher. At NTC, the use of 8T instead of 6T SRAM cells can reduce the system-level SNM and SER by 14% and 22%, respectively. Besides, we observe that we can find the right balance between performance and reliability by using an appropriate cache organization at NTC which is different from the super threshold.

Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in 130 nm CMOS technology. The QUCCE 10T and 12T are about $2\times $ and $3.4\times $ the minimum critical charge of the conventional 6T, respectively. Compared with most of the considered state-of-the-art SRAM cells, both QUCCE 10T and 12T have comparable or better soft error tolerance, time performance, read static noise margins, and hold static noise margins, and besides, QUCCE 10T also has similar or lower costs in terms of area and leakage power. The QUCCE 10T is designed for high-density SRAMs at the nominal supply voltage. Furthermore, the QUCCE 12T saves more than 50% the read access time compared with most of the referential cells including the 6T, making it suitable for high speed SRAM designs, and it also has the best read margin, except for the traditional 8T, in terms of $\mu /\sigma $ ratio in the near threshold voltage region among all the other considered cells which nearly have no write failure in that region. Hence, the QUCCE 12T is a promising candidate for future highly reliable terrestrial low-voltage applications.

Data-Pattern Enabled Self-Recovery Low-Power Storage System for Big Video Data

The growing popularity of powerful mobile devices such as smart phones and tablet devices has resulted in the exponential growth of demand for video applications. However, due to the large video data size and intensive computation, mobile video applications require frequent embedded memory access, which consumes a large amount of power and limits battery life. In this paper, we present a low-cost self-recovery video storage system by investigating meaningful data patterns hidden in big video data, by introducing data mining techniques to the hardware design process. We propose a two-dimensional data-pattern approach to explore horizontal data-association and vertical data-correlation characteristics. Such data relationship discovery and pattern identification enable a new dimension for the hardware design space and bring self-recovery ability to memories in the presence of bitcell failures. Based on the identified optimal data patterns, we present a low-cost and efficient SRAM design to enable data self-recovery at low voltages. A 45nm 32 kb SRAM is implemented that delivers good video quality at near-threshold voltage (0.5 V) with negligible area overhead (7.94 percent).

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

On Mathematical Models of Optimal Video Memory Design

The big video data size today imposes huge pressure on storage. The variation and aging induced memory failures significantly influence the video output quality. Recently, researchers have developed different memory designs for videos, deep learning, and other data-intensive applications, which enables better energy-quality tradeoffs with design constraints. Unfortunately, designing memory has been proven to be a very challenging problem due to: 1) various design constraints; 2) multiple memory bitcell design options; and 3) challenging layout integration and cost analysis using different memory technologies. In this paper, we develop novel mathematical models for optimizing embedded video memory design without applying a time-consuming and laborious ASIC design process. The problems are formulated as nonlinear programs and integer linear programs. Different SRAM designs and hybrid SRAM and DRAM designs are considered in our models. The results of the numerical studies show that by applying our proposed method the average mean square error of the video storage can be greatly reduced, even by more than 90% in many cases.

Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit

Lowering power consumption and increasing the noise margin have become the two most important aspects to be considered in SRAM design. Additionally, a stable operation with good memory retention capability has gained greater importance in obtaining good yield at low-voltage and low-power SRAM designs, due to the fact that parameter variations play a major role in scaled technologies. In this paper, the 6T SRAM, 7T low power SRAM and 7T multi threshold low power SRAM designs are designed, to incorporate power gating technique. The architecture of each of the SRAM designs and their working are analyzed thoroughly. The outputs of the read, write and hold operations with transient response are observed and the power dissipation and static noise margin (SNM) of the each of the SRAM cells is calculated and compared. The paper also presents new power reduction solution through the cell control circuit which reduces the unwanted and spurious switching activities during read and writes operations. The paper demonstrates the reduction of the power con- sumption through the use of cell control circuit.

Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis

This paper presents two different topologies of 11T SRAM cells with fully half-select-free robust operation for bit-interleaving implementation. The proposed 11T-1 and 11T-2 cells successfully eliminate Read disturb and Write half-select disturb and also improve the Write-ability by using power-cutoff and write “0”/ “1” only techniques. The 11T-1 and 11T-2 cells achieve $1.83 \times $ and $1.7 \times $ higher write-yield while both achieve approximately $2 \times $ higher read-yield as compared with 6T cell (at ${V}_{DD} = 0.9$ V). The proposed 11T-1 cell also shows 13.6% higher mean Write-margin (WM) compared with existing 11T cell. Both the proposed cells successfully eliminate floating node condition encountered in earlier power cut-off cells during write half-select. Monte-Carlo simulation confirms low-voltage operation without any additional peripheral assist circuits. We also present a comparative analysis of Bias Temperature Instability reliability impacting the SRAM performance in a predictive 32nm high-k metal gate CMOS technology. Under static stress, the Read Static Noise Margin (RSNM) reduces for all cells. However, 11T-1 and 11T-2 cells improve RSNM by 2.7% and 3.3% under relaxed stress of 10/90. Moreover, the proposed 11T-1 (11T-2) cell improves WM by 7.2% (13.2%), reduces write power by 28.0% (20.4%) and leakage power by 85.7% (86.9%), degrades write delay by 38.1% (23.3%) without affecting read delay/power over a period of 108 seconds (approx. 3 years). The 11T-1 (11T-2) cell exhibits 4.8% higher (2% lower) area overhead as compared to earlier 11T cell. Hence, the proposed 11T cells are an excellent choice for reliable SRAM design at nanoscale amidst process variations and transistor aging effect and can also be used in bit-interleaving architecture to achieve multi-cell upset immunity.