High Speed Novel Design of Sram for Highly Reliable Applications

Abstract

Modern ICs are enormously complicated due to decrease in device size and increase in chip density involving several millions of transistors per chip. The rules for manufactured leads to a tremendous increase in complexity due to the amount of power dissipation are increased. In this paper, the design of novel SRAM is implemented for the highly reliable applications. For high-speed memory applications such as cache, a SRAM is often used. Power consumption is the key parameter for an SRAM memory design (SRAM). New tag generation system designed for integrity checking of SRAM. A single read operation to a crossbar SRAM that can be used for integrity checking. Reliability of the system is measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage.