Design Of Quantum-dot Cellular Automata Circuits Research Articles

Notice of Violation of IEEE Publication Principles: Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate

Notice of Violation of IEEE Publication Principles “Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate” by Suhaib Ahmed and Syed Farah Naz in IEEE Transactions on Circuits and Systems II: Express Briefs After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. “Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata” By Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng and Guangjun Xie in Journal of Circuits, Systems, and Computers, Vol. 28, No. 8, 2017 The advantages such as high operating frequency (in the range of few THz), low power dissipation, small size and high density in the nano regime has led to the application of Quantum dot Cellular Automata (QCA) in designing various digital circuits. In this brief, an ultra-efficient two input XOR gate design in QCA is proposed. It is a single layer design consisting of only 9 cells with no crossover and operating on cell to cell interaction. The functionality of the proposed gate has been verified at both physical and simulation level. In addition to this, fault tolerance to single cell missing defect, single cell addition defect and single cell displacement defect of the proposed XOR gate has also been presented. Based on the performance evaluation, it is seen that the proposed XOR gate has least cell count, least area and least latency which in turn leads to least circuit cost. Also, the proposed design dissipates least energy. The applicability of proposed XOR gate has also been investigated by designing various cost efficient digital circuits such as full adder, parity checker, etc.

Methodology for Automated Design of Quantum-Dot Cellular Automata Circuits

Quantum-dot Cellular Automata (QCA) provide very high scale integration potential, very high switching frequency, and have extremely low power demands, which make the QCA technology quite attractive for the design and implementation of large-scale, high-performance nanoelectronic circuits. However, state-of-the-art QCA circuit designs were not derived by following a set of universal design rules, as is the case of CMOS circuits, and, as a result, it is either impossible or very difficult to combine QCA circuit blocks in effective large-scale circuits. In this paper, we introduce a novel automated design methodology, which builds upon a QCA specific universal design rules set. The proposed methodology assumes the availability of a generic QCA crossbar architecture and provides the means to customize it in order to implement any given logic function. The programming principles and the flow of the proposed automated design tool for crossbar QCA circuits are described analytically and we apply the proposed automated design method for the design of both combinatorial and sequential circuits. The obtained designs demonstrate that the proposed method is functional, easy to use, and provides the desired QCA circuit design unification.

A general and efficient clocking scheme for majority logic in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is a nanotechnology with characteristics of high speed, high density, and low power consumption to be one of the strong alternatives to replace traditional CMOS in the future in theory. Its primitive is a majority gate, instead of AND/OR logic in CMOS, which can reduce the complexity of a system and thus its overhead. In this paper, a general and efficient clocking scheme to facilitate the design of circuits using majority gates in QCA is proposed as their scale extends. Each clock zone in this scheme is an octagon adjacent to the other three zones. This results in four input and two output directions in clock zones 0 and 2 to design circuits with majority gates, two input and four output directions in clock zones 1 and 3 to improve the flexibility of circuit routing. Besides, this scheme utilizes the flexible feedback paths for sequential circuits, equivalent clock zones, and elastic QCA wires for efficiently wiring circuits. This paper then takes a one-bit full adder and an SR-latch as examples to show the generality and efficiency of the proposed clocking scheme in designing combinational and sequential circuits, respectively. An arithmetic unit is also taken as an example to illustrate its high expansibility in designing larger circuits. Experimental results show that the proposed clocking scheme is more suitable for QCA circuit design in contrast to previous clocking schemes.

Regular clocking-based Automated Cell Placement technique in QCA targeting sequential circuit

Quantum-dot cellular automata (QCA) is field-coupled nanotechnology that achieves high device density, high switching speed, and low power dissipation. The flow of information within QCA is fully controlled by the position of the electrons only. A proper cell placement and its respective clock zone for the correct logic operation become the utmost design requirement. Insufficient research in this direction and appropriate use of regular clocking requires rigorous research in this area. An appropriate routing channel to adopt a stable and steady underlying clock scheme plays an essential role in positioning QCA cells. This paper presents a systematic placement of QCA cells targeting sequential logic, which makes efficient use of the underlying regular clocking scheme. The proposed method is verified by implementing the SR and D flip flop incorporating the USE clocking scheme. The effectiveness of the proposed cell positioning algorithm is reported. A significant performance improvement is observed, which advocates the importance of such a scheme in QCA circuit design.

Systematic cell placement in quantum‐dot cellular automata embedding underlying regular clocking circuit

Quantum-dot cellular automata (QCA) is gaining worldwide popularity due to its higher device concentration, lower power indulgence, and better switching speed. The information flows in QCA with the polarization state defined by the placement of electrons instead of current flow. The cell interaction principle under the influence of the clocking zone controls the cell placement during QCA circuit design. Most of the designs reported so far used random cell placement, which has no fabricating sense. Moreover, it is equally important for a cell placement algorithm to follow a realistic, regular underlying clocking scheme to maintain proper routing channels. In this regard, a systematic cell placement for the combinational logic circuit in QCA is proposed using the widely accepted underlying regular clocking scheme, universal, scalable and efficient (USE). The proposed method traverses all possible paths of a combinational logic circuit from output to input to build the desired circuit generating the automatic cell layout. A grid of clock zone of USE clock scheme is considered in the initial layout driving different paths of the circuit and finally evolves as the desired circuit. The generated automatic QCA layouts are competitive in occupied area, delay, and its cell count, which advocates the significance of such a scheme.

Spars: A Full Flow Quantum-Dot Cellular Automata Circuit Design Tool

Quantum-dot cellular automata (QCA) is an emerging nanotechnology to be a possible candidate for CMOS technology. There exist separate tools and algorithms for various kinds of design and simulation requirements of QCA circuits, but still lacks a unified software platform that can cover all the design stages. This brief describes a project that composes the state-of-the-art algorithms into a QCA circuit design tool suite named spars. The target of the project is establishing a fluent design flow that is similar to the CMOS circuit design process. Specifically, a new depth-oriented synthesis algorithm based on the majority inverter graph (MIG) is proposed. Besides, good software engineering ensures the easy extendability of spars, so that it provides a better starting point for the development of software design and circuit design in QCA.

Implementing Logical Circuits with Four Phase Quantum Dot Cellular Clock using QCA Designer

Quantum Dot Cellular Automata (QCA) is treated as a most promising technology after CMOS techniques. The major advantages of QCA techniques are faster speed, lower energy consumption and smaller size. The implementation of clocks play very big role in the effective design of QCA circuits. In this paper, a QCA circuit is designed using the concept of QCA clocks. The proposed study describes a new method of implementing the logical function with power depletion analysis. The proposed logical function uses total number of 57 cells in which the area of each cell 372 nm2. The energy dissipation in this implementation is 18.79 meV and the total acquired area is 0.192 μm2. The proposed circuit is implemented utilizing QCA Designer. The proposal is excellent in the realization of nano-scale computing with minimal power utilization. The results are compared with the existing approaches and improvements of 6% in the area required and 7% in the number of cells are achieved.

CFE: a convenient, flexible, and efficient clocking scheme for quantum‐dot cellular automata

Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit designs. The circuits in QCA have been extensively studied, which suffer from negative impacts due to the limits of the manual design process, even for a modest complexity. In the process of QCA circuit design, the problems caused by clock distribution and long transmission lines have to be considered. In order to solve such problems, some researchers have proposed several clock schemes and expected to realise electronic design automation. These clock schemes, however, have drawbacks; the most important one is the limitation of flexibility on designing complex circuits. In this regard, this study proposes a convenient, flexible, and efficient (CFE) clocking scheme by using diamond structures for clock zones, each of which has the same neighbouring clock zone and four information transmission directions. It has main advantages of existing clocking schemes and can commendably increase the flexibility in circuit design process. In order to show the suitability of the proposed CFE scheme using standard clock mechanism in QCA, several types of circuits proposed in this study reveal its advantages in comparison with an existing state-of-the-art clocking scheme.

Design of testable reversible latches by using a novel efficient implementation of Fredkin gate

ABSTRACTEnergy dissipation caused by information loss in irreversible computations will be an important limitation for the development of nano-scale circuits in the near future. Reductions in energy dissipation comprise one of the important goals of nanotechnology-based methods, including Quantum dot Cellular Automata (QCA), and so it is desirable to consider reversibility in the design of QCA circuits. In this research, a novel reversible Fredkin gate based on QCA is proposed, which is more efficient and less complex than the conventional Fredkin gate. Conservative reversible logic is parity preserving; hence, any permanent or transient fault can be caused a mismatch between the inputs and the outputs and can be concurrently detected if a reversible circuit is implemented with the conservative Fredkin gate. A single missing/additional cell defect is investigated in the proposed Fredkin gate and fault patterns are presented. To demonstrate the efficiency of the proposed design, some testable reversible sequential elements, such as D-latch, JK-latch, T-latch and SR-latch, are designed by using it. Our proposed concurrent testable designs greatly reduce the occupied area and maximise the circuit density in comparison with previously reported designs. The proposed designs are simulated and verified using QCA Designer ver.2.0.3 and HDLQ.

An Ultra-Low Power Parity Generator Circuit Based on QCA Technology

Quantum-dot cellular automata (QCA) technology is one of the emerging technologies that can be used for replacing CMOS technology. It has attracted significant attention in the recent years due to its extremely low power dissipation, high operating frequency, and a small size. In this study, we demonstrate an n-bit parity generator circuit by utilizing QCA technology. Here, a novel XOR gate is used in the synthesis of the proposed circuit. The proposed gate is based on electrostatic interactions between cells to perform the desired function. The comparison results demonstrate that the designed QCA circuits have advantages compared to other circuits in terms of cell count, area, delay, and power consumption. The QCADesigner software, as widely used QCA circuit design and verification, has been used to implement and to verify all of the designs in this study. Power dissipation has been computed for the proposed circuit using accurate QCAPro power estimator tool.

An Efficient Design of DCT Approximation Based on Quantum Dot Cellular Automata (QCA) Technology

Optimization for power is one of the most important design objectives in modern digital image processing applications. The DCT is considered to be one of the most essential techniques in image and video compression systems, and consequently a number of extensive works had been carried out by researchers on the power optimization. On the other hand, quantum-dot cellular automata (QCA) can present a novel opportunity for the design of highly parallel architectures and algorithms for improving the performance of image and video processing systems. Furthermore, it has considerable advantages in comparison with CMOS technology, such as extremely low power dissipation, high operating frequency, and a small size. Therefore, in this study, the authors propose a multiplier-less DCT architecture in QCA technology. The proposed design provides high circuit performance, very low power consumption, and very low dimension outperform to the existing conventional structures. The QCADesigner tool has been utilized for QCA circuit design and functional verification of all designs in this work. QCAPro, a very widespread power estimator tool, is applied to estimate the power dissipation of the proposed circuit. The suggested design has 53% improvement in terms of power over the conventional solution. The outcome of this work can clearly open up a new window of opportunity for low power image processing systems.

Multiple Missing Cell Defect Modeling for QCA Devices

Considering the limitations of CMOS technology, the Quantum-dot Cellular Automata (QCA) is emerging as one of the alternatives for Integrated Circuit (IC) Technology. A lot of work is being carried out for design, fabrication and testing of QCA circuits. In this paper, we have worked on defect analysis, fault models development and deriving various properties for QCA Majority Voter (MV) to effectively generate the test patterns for QCA circuits. It has been shown that unlike CMOS technology, single missing cell consideration is not enough for QCA technology. We have presented that the Multiple Missing Cell (MMC) defect, which is very natural at nanoscale, causes the sizable difference in functionality compared to Single Missing Cell consideration described in literature, and hence, must be considered while test generation. The proposed MMC is supported by exhaustive simulation results as well as kink energy based mathematical analysis. Further, Verilog fault models are proposed which can be used for the functional, timing verification and activation of faults caused by MMC defect. The effect of MMC on output is analyzed in stand-alone MV as well as when MV is a part of circuit. At the end, we have proposed the test properties of MV when being used as MV itself, as AND gate or OR gate. These properties may be further helpful in development of test generation algorithms.

A systematic approach towards fault-tolerant design of QCA circuits

Quantum-dot cellular automata (QCA) has emerged as a crucial alternative to CMOS technology in the recent years. However, the main hindrance in advancement of QCA technology is that it suffers from various types of manufacturing defects and variations. Several cell misplacement defects introduced in the deposition phase of manufacturing process of QCA have been found to be frequent. Manifestation of such defects may greatly impact the functionality and performance of QCA circuits. A few designs of various QCA modules based on some ad-hoc tricks have shown to diminish the negative effect of defects significantly, thereby making the design fault(defect)-tolerant. However, in the absence of proper insights, they fail to provide any guideline towards fault-tolerant design of QCA circuits in general. Moreover, these designs mostly compromise a lot with the other important design parameters such as area, latency. In this paper, we propose a set of comprehensive guidelines that will elucidate the path for systematic design of practical fault-tolerant circuits in QCA. The guidelines have been derived based on some critical observations made during extensive simulation experiments carried out in QCADesigner followed by theoretical explanation. The usage of the proposed guidelines has been illustrated by designing an adder circuit.

A Fault-Tolerant and Efficient XOR Structure for Modular Design of Complex QCA Circuits

Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits.

Programmable Crossbar Quantum-Dot Cellular Automata Circuits

Quantum-dot fabrication and characterization is a well-established technology, which is used in photonics, quantum optics, and nanoelectronics. Four quantum-dots placed at the corners of a square form a unit cell, which can hold a bit of information and serve as a basis for quantum-dot cellular automata (QCA) nanoelectronic circuits. Although several basic QCA circuits have been designed, fabricated, and tested, proving that quantum-dots can form functional, fast and low-power nanoelectronic circuits, QCA nanoelectronics still remain at its infancy. One of the reasons for this is the lack of design automation tools, which will facilitate the systematic design of large QCA circuits that contemporary applications demand. Here we present novel, programmable QCA circuits, which are based on crossbar architecture. These circuits can be programmed to implement any Boolean function in analogy to CMOS field-programmable gate arrays and open the road that will lead to full design automation of QCA nanoelectronic circuits. Using this architecture we designed and simulated QCA circuits that proved to be area efficient, stable, and reliable.

An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata

In recent years, majority-logic received significant attention as a synthesis approach for large Boolean functions. This logic is easily implemented in Quantum-dot cellular automata (QCA) technology which is emerging as an alternative to CMOS technology. In fact, majority logic gate serves as the basic logic unit in the digital design of QCA circuits. This paper introduces a synthesis technique for implementing totally symmetric Boolean functions using majority logic. First, a simple regular module is designed to synthesize unate symmetric functions. The structure uses 3-input majority gates. General symmetric Boolean functions are then realized following a unate decomposition method. We study the synthesis of some well known benchmark symmetric functions using the proposed method. Comparison with existing synthesis approaches confirms the efficacy of our method.

Reliability-aware design for programmable QCA logic with scalable clocking circuit

The limitations of complementary metal---oxide---semiconductor (CMOS) technology on the nanoscale will prevent continuation of the current scaling trends in very large-scale integration (VLSI). Quantum-dot cellular automata (QCA) are one of the emerging nanotechnologies, conceived as a viable alternative to CMOS circuits, offering exceptionally high integration density, impressive switching frequency, and remarkably low power characteristics. However, fabrication issues and susceptibility to high error rates have raised many questions regarding this technology, leading to the search for efficient and scalable methods for design of QCA circuits. In this regard, this work targets a generic, reliable and programmable (RP) architecture for QCA with hybrid cell orientation. An efficient, easily manufacturable, and scalable clocking scheme is proposed towards the design of fault-tolerant QCA architectures. The functionality and defect tolerance of a five-input majority voter with RP structure (RMV) are investigated under cell deposition defects. Simulation results demonstrate that the proposed RP structure is more reliable than the conventional design. Besides reliability, the most striking characteristic of this logic is that it is completely programmable to perform various logic functions, reducing the requirement for disparate logic for large circuits. Comprehensive analysis of its programmable feature is applied to achieve a full adder, which extends its reliability to circuit level. The design of the QCA layout, as well as functional verification of the proposed design, is performed using QCADesigner.

Design and analysis of new fault-tolerant majority gate for quantum-dot cellular automata

Due to its ultrasmall size and extremely low power consumption, quantum-dot cellular automata (QCA) technology represents a promising alternative to semiconductor transistors at the nanoscale. Nevertheless, the design of QCA circuits is limited by their high defect rate during fabrication, making fault-tolerant QCA structures a popular research topic. The aim of this work is to design a new fault-tolerant QCA majority gate based on a $$3\times 5$$3×5 tile. The majority gate guarantees good fault tolerance under single cell and double cell missing defects compared with several previous structures. The functional results when adopting the polarization and kink energy of the proposed majority gate under such single cell and double cell deposition defects are fully investigated. Besides, a series of new fault-tolerant adders are implemented based on the fault-tolerant majority gates. To evaluate the performance of the proposed adders, a thorough comparison versus previous adders with respect to fault tolerance, cell number, area, and delay is carried out. The results indicate that the proposed design can reach a high level of fault tolerance, and perform rather well in terms of other properties. For simulation analysis, the QCADesigner tool is used to check the functionality of all circuits.

Wire crossing constrained QCA circuit design using bilayer logic decomposition

Quantum-dot cellular automata (QCA) seek potential benefits over CMOS devices such as low-power consumption, small dimensions, and high-speed operation. Two prominent QCA concerns of wire crossing complexity and circuit robustness are addressed by developing a three-step bilayer logic decomposition (BLD) methodology to design QCA-based logic circuits. The partitioning of QCA computing operations into logic layers realises considerable improvements in complexity, area, and modularity metrics. Moreover, since larger circuits are divided into two increasingly disjoint sub-planes, verification of the functionality of the design becomes compartmentalised. Design capability of the proposed approach is illustrated and analysed by implementing an area-efficient full comparator (FC) based on a novel logic realisation. The resulting 1-bit FC achieves 32% improvement in complexity metrics in comparison with the previous optimal QCA-based FC. The related waveforms used in verification of the BLD-generated FC which are obtained by the QCADesigner simulation tool are discussed as a motivating example of the BLD methodology.

Two-layer synchronized ternary quantum-dot cellular automata wire crossings

Quantum-dot cellular automata are an interesting nanoscale computing paradigm. The introduction of the ternary quantum-dot cell enabled ternary computing, and with the recent development of a ternary functionally complete set of elementary logic primitives and the ternary memorizing cell design of complex processing structures is becoming feasible. The specific nature of the ternary quantum-dot cell makes wire crossings one of the most problematic areas of ternary quantum-dot cellular automata circuit design. We hereby present a two-layer wire crossing that uses a specific clocking scheme, which ensures the crossed wires have the same effective delay.