A systematic approach towards fault-tolerant design of QCA circuits

Abstract

Quantum-dot cellular automata (QCA) has emerged as a crucial alternative to CMOS technology in the recent years. However, the main hindrance in advancement of QCA technology is that it suffers from various types of manufacturing defects and variations. Several cell misplacement defects introduced in the deposition phase of manufacturing process of QCA have been found to be frequent. Manifestation of such defects may greatly impact the functionality and performance of QCA circuits. A few designs of various QCA modules based on some ad-hoc tricks have shown to diminish the negative effect of defects significantly, thereby making the design fault(defect)-tolerant. However, in the absence of proper insights, they fail to provide any guideline towards fault-tolerant design of QCA circuits in general. Moreover, these designs mostly compromise a lot with the other important design parameters such as area, latency. In this paper, we propose a set of comprehensive guidelines that will elucidate the path for systematic design of practical fault-tolerant circuits in QCA. The guidelines have been derived based on some critical observations made during extensive simulation experiments carried out in QCADesigner followed by theoretical explanation. The usage of the proposed guidelines has been illustrated by designing an adder circuit.