Microprocessor Design Research Articles

Teaching content model for designing digital systems of power grid relay protection and automation

It was found that the effective formation of conceptual-analytical and productive-synthetic levels of formation of professional knowledge and skills regarding the design of digital systems of power grid relay protection and automation is possible with the systematic development and use of a generalized model of the teaching content. Based on the study of information models of technical systems, a feature model was adopted as a basic invariant, which includes a set of features of the purpose, construction, principle of operation and parameters of the technical system. It was found that the design process of digital systems of power grid relay protection and automation can be conventionally divided into three stages, namely, the development of the design task, the direct implementation of the design, and the determination of the parameters of operation. Causal chains of knowledge that form the basis of problem solving at these three stages are determined. It was found that the methods of step-by-step decomposition and aggregation are key in building the content of teaching the design of digital systems of power grid relay protection and automation based on causal chains of knowledge. A generalized model of the teaching content design of digital systems of power grid relay protection and automation based on causal chains of knowledge is substantiated. According to the generalized model, the teaching content design of specific microprocessor l systems of power grid relay protection and automation has been developed. With the help of experimental verification, the effectiveness of the teaching content design of digital systems of relay protection and automation based on causal chains of knowledge has been proven. The results of the research can be used in the educational process of professional training of future engineers in the specialty 141 Electric power, electrical engineering and electromechanics.

Approximate Computing Based Low-Power FPGA Design for Big Data Analytics in Cloud Environments

As cloud computing continues to evolve, the demand for scalable and energy-efficient infrastructure to handle extensive applications becomes paramount. Traditional transistor scaling and microprocessor design methods no longer suffice to meet the growing scale of cloud usage. This research explores the potential of approximate computing (AC) as an innovative solution to these challenges, particularly in high-demand computational settings. AC, known for its ability to make controlled accuracy trade-offs, is identified as a key strategy for improving both the performance and energy efficiency of cloud infrastructure, with a focus on low-power Field-Programmable Gate Array (FPGA) designs. This paper introduces novel methodologies that harness the strengths of AC, emphasizing its application in neural-based and machine-learning techniques for energy-efficient solutions. By targeting the performance of AC, especially in varied application domains and complex data mining scenarios, we propose two groundbreaking approaches that significantly enhance computational speed and reduce energy consumption. Our empirical analysis demonstrates notable improvements over existing techniques, highlighting the effectiveness of AC in optimizing cloud infrastructure. The proposed model on FPGA through cloud computing attains substantial elevation rates by 89 % and energy reduction by 122%, which had been good outcomes. This study not only confirms the benefits of integrating AC with low-power FPGA designs for cloud environments but also sets a new benchmark for future research in achieving more sustainable and efficient cloud computing via VLSI FGPA design analysis solutions.

Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs

Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs

Microprocessor Design Using COPRAS Method

Introduction: A microprocessor is a computer and An important part of the structure, Without it, on your computer, Nothing can be done. it is a programmable device, It does some arithmetic on the input and logical operations and the desired output creates. In simple words, Microprocessor is on a chip It is a digital device Instructions from memory. Get them and decode them can run and give results. Fundamentals of Microprocessor. In a microprocessor machine language Take some steps that activate them, to the processor That's what it should do says Microprocessor instruction Three basics when implementing Doing things: Its addition, Subtraction, multiplication, division, and some logic functions Arithmetic and Logic Unit (ALU) makes use of. New Microprocessors are floating point Functions in numbers are doing In microprocessors The data in is from one location Can be moved to another location. It is a Program Counter (PC). Contains the registry, which Based on the value of the system address of the next instruction Stores, the microprocessor from place to place Jumps and makes decisions.Research significance: For microprocessor design, this Description Various semiconductors In device fabrication processes Made using some, Consequently in a chip carrier A drop in binding occurs. This chip carrier is then printed. Solder on the circuit board (PCB). done or in the socket is inserted. New microprocessor or microcontroller unit, To make the process flow logically Some general steps can be followed. These few steps make it even easier for small manageable tasks can be separated. A new microprocessor General steps for designing. A must-have in the new app is the determination of skills. required Data path to handle capabilities Set up. Machine code Instructional Design (ISA) Define. data path Create the necessary logic to control.Methodology: An analysis of the COPRAS method in this complex proportionality assessment (COPRAS) system in 1994 showed that the index values used to assess the Gavaskar, Kalkaska, and sarka introduced at this time increased and decreased. Alternatives: Poor life recycled products market, poor consumer perception of recycled products, poor supplier commitment, the poor success of curbside pickup. Evaluation Option: Finance Team, Engagement / Support, Infrastructure Team, Knowledge Team, Environment Team.Alternative: CISC is Intel 386, Intel 486, Pentium, EPIC is IA-64, DEC Alpha 21164. Evaluation preference: Feature size (micron), Supply voltage (V), Die size (mm2), DRAM bits/chip (m).Results: from the result, it is seen that CISC Intel 386 is got the first rank whereas DEC Alpha 21164 is having the lowest rank.

Teaching computer architecture by designing and simulating processors from their bits and bytes.

Teaching computer architecture (Comp-Arch) courses in undergraduate curricula is becoming more of a challenge as most students prefer software-oriented courses. In some computer science/engineering departments, Comp-Arch courses are offered without the lab component due to resource constraints and differing pedagogical priorities. This article demonstrates how students working in teams are motivated to study the Comp-Arch course and how instructors can increase student motivation and knowledge by taking advantage of hands-on practices. The teams are asked to design and implement a 16-bit MIPS-like processor with constraints as a specific instruction set, and limited data and instruction memory. Student projects include following three phases, namely, design, desktop simulator implementation, and verification using hardware description language (HDL). In the design phase, teams develop their Comp-Arch to implement specified instructions. A range of designs resulted, e.g., (a) a processor with extensive user-defined instructions resulting in longer cycle times (b) a processor with a minimal instruction set but with a faster clock cycle time. Next, teams developed a desktop simulator in any programming language to execute instructions on the architecture. Finally, students engage in Verilog Hardware Description Language (HDL) projects to simulate and verify the data-path designed during the initial phase. Student feedback and their current understanding of the project were collected through a questionnaire featuring varying Likert scale questions, some with a ten-point scale, and others with a five-point scale. Results of the survey show that the hands-on approach increases students' motivation and knowledge in the Comp-Arch course, which is centered around computer system design principles. This approach can also be effectively extended to related courses, such as Microprocessor Design, which delves into the intricacies of creating and implementing microprocessors or central processing units (CPUs) at the hardware level. Furthermore, the present study demonstrates that interactions, specifically through peer reviews and public presentations, between students in each phase increases their knowledge and perspective on designing custom processors.

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration

Microarchitecture parameters tuning is critical in the microprocessor design cycle. It is a non-trivial design space exploration (DSE) problem due to the large solution space, cycle-accurate simulators’ modeling inaccuracy, and high simulation runtime for performance evaluations. Previous methods require massive expert efforts to construct interpretable equations or high computing resource demands to train black-box prediction models. This article follows the black-box methods due to better solution qualities than analytical methods in general. We summarize two learned lessons and propose BOOM-Explorer accordingly. First, embedding microarchitecture domain knowledge in the DSE improves the solution quality. Second, BOOM-Explorer makes the microarchitecture DSE for register-transfer-level designs within the limited time budget feasible. We enhance BOOM-Explorer with the diversity-guidance, further improving the algorithm performance. Experimental results with RISC-V Berkeley-Out-of-Order Machine under 7-nm technology show that our proposed methodology achieves an average of 18.75% higher Pareto hypervolume, 35.47% less average distance to reference set, and 65.38% less overall running time compared to previous approaches.

Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers

Reliability evaluation of a microprocessor design may reveal vulnerable silicon areas that require protection against faults, but also hardware structures that are inherently more resilient to faults. In this work, we revisit the concept of system vulnerability stack by analyzing the anatomy of fault effects across the abstraction layers and identify the sources of error in well-established transient fault vulnerability evaluation methodologies. By providing insights for all distinct system layers, we showcase that the evaluation should take into consideration all faults that arrive from the underlying hardware as well as their distribution. We additionally quantify the level of error in a PVF estimation that can be attributed to the microarchitecture and the architecture. Current established methodologies fail to capture these aspects and can potentially lead to misleading findings. We experimentally show how PVF estimation can follow opposite (and thus misleading) trends compared to the correct, full-stack Architectural Vulnerability Factor (AVF) estimation and explain the reasons why the higher-level methodologies provide diverging results by showing the anatomy of faults manifestation across the layers. Our experiments are performed on an Armv8 microprocessor model, using different input datasets to thoroughly demonstrate our insights.

Features of analysis and selection of microprocessors in modern control systems

The article discusses the results of a brief retrospective review of the current microprocessors in control systems and the main directions of their development. The main requirements and selection criteria presented at the stage of the microprocessor design process in modern control systems, classification and architectural features of microprocessors are described. In addition, the «pipeline» processing method for maximizing processor performance, features of the analysis and selection of microprocessors in modern control systems using various architectural solutions for the elimination of contradictions arising in it related to conflicts are studied. According to the «pipeline» principle, three main types of processor architecture (VLIW – Very Long Instruction Word) with superscalar and multiple computing devices working in parallel are defined - depending on data, management and structural conflicts. Therefore, their use in VLIW processors and the limitation of their application in the field of scientific research is justified, due to the fact that the source codes are transmitted in a «closed» form. The main advantage of superscalar microprocessors is the independence of program-executable codes from their structure and the possibility of their execution on any processor models. In addition, the features of the EPIC architecture are described, which combines the advantages of the two different architectural solutions considered.

STRV — a radiation hard RISC-V microprocessor for high-energy physics applications

While microprocessors are used in various applications, they are precluded from the use in high-energy physics applications due to the harsh radiation present. To overcome this limitation a microprocessor design must withstand high doses of radiation and mitigate radiation induced soft errors. A TMR protection scheme is applied to protect a RISC-V microprocessor core against these faults. The protection of the integrated SRAM by an independent scrubbing algorithm is discussed. Initial irradiation results and power consumption measurements of the radiation-resistant RISC-V microprocessor implemented in 65 nm CMOS technology are presented.

Special Issue on Artificial Intelligence at the Edge

The papers in this special section explore cutting edge research on topics that combine artificial intelligence with edge computing, relating to the design, performance, or application of microprocessors and microcomputers.

Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case Study

State-of-the-art modern microprocessor and domain-specific accelerator designs are dominated by data-paths composed of regular structures, also known as bit-slices. Random logic placement and routing techniques may not result in an optimal layout for these data-path-dominated designs. As a result, implementation tools such as Cadence’s Innovus include a Structured Data-Path (SDP) feature that allows data-path placement to be completely customized by constraining the placement engine. A relative placement file is used to provide these constraints to the tool. However, the tool neither extracts nor automatically places the regular data-path structures. In other words, the relative placement file is not automatically generated. In this paper, we propose a semi-automated method for extracting bit-slices from the Innovus SDP flow. It has been demonstrated that the proposed method results in 17% less density or use for a pixel buffer design. At the same time, the other performance metrics are unchanged when compared to the traditional place and route flow.

Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells

Micro-processor designs have become a revolutionary technology almost in every industry. They brought the reality of automation and also electronic gadgets. While trying to improvise these hardware modules to handle heavy computational loads, they have substantially reached a limit in size, power efficiency, and similar avenues. Due to these constraints, many manufacturers and corporate entities are trying many ways to optimize these mini beasts. One such approach is to design microprocessors based on the specified operating system. This approach came to the limelight when many companies launched their microprocessors. In this paper, we will look into one method of using an arithmetic logic unit (ALU) module for internet of things (IoT)-enabled devices. A specific set of operations is added to the classical ALU to help fast computational processes in IoT-specific programs. We integrated a compression module and a fast multiplier based on the Vedic algorithm in the 16-bit ALU module. The designed ALU module is also synthesized under a 32-nm HVT cell library from the Synopsys database to generate an overview of the areal efficiency, logic levels, and layout of the designed module; it also gives us a netlist from this database. The synthesis provides a complete overview of how the module will be manufactured if sent to a foundry.

RTL Design of CISC CPU IP Core

Abstract: Recent developments on programmable logic technology had promoted the microprocessor design task from big companies targeting the mass market to the everyday designer as intellectual property (IP) cores toward the system on-a-chip (SOC) approach. This paper shows the VHDL IP 8-bit CISC microprocessor core development which is intended as an open core for teaching applications in the digital systems laboratory. The core is fully open and therefore, the user can have access to all internal signals as well as the opportunity to make changes to the structure itself which is very useful when lecturing microprocessor design. The main advantages of the present core, compared with commercially available equivalent cores, are that it is not vendor sensitive allowing its implementation in almost any FPGA family and being an open core, it can be fully monitored and modified to fit specific design constrains. Several tests were performed to the microprocessor core, including an embedded microcontroller with RAM, ROM and I/O capabilities. The present development includes a meta-assembler and linker to embed user programs in a ROM, which is automatically generated as a VHDL description

Grammar-based fuzz testing for microprocessor RTL design

Recently, agile hardware design (AHD) methodology has been proposed to alleviate the productivity crisis brought by the growing complexity of modern microprocessor design. One of the key techniques in AHD is the adoption of hardware construction languages (HCLs) which have greatly improved the design productivity. However, the adoption of HCLs arises new challenges to design verification. In this paper, we proposed an enhanced coverage-directed dynamic verification technique for microprocessor RTL designs modeled using PyRTL HCL. The intention of the proposed method is to achieve higher coverage in dynamic verification.The proposed method is a hybrid between symbolic simulation and grammar-based fuzz testing, which offsets the disadvantages of each separate technique. We define Full Multiplexer Toggle Coverage (FMTC) to trace and provide feedback to the verification process. The achievement of high coverage is obtained by interleaving symbolic simulation and grammar-based fuzz testing passes. The symbolic simulation pass is used to generate tests that direct the testing to untouched corners, while the grammar-based fuzz testing pass is used to leverage test generation tasks and to enable the method to deal with microprocessor designs with a specific instruction set architecture (ISA). In addition, to further reduce testing cost, we propose a test compression technique to compress the generated test instructions by dropping redundant instructions.Finally, we implement all the enhancements in a test generation tool, named MPFuzz. Experimental results show that MPFuzz can efficiently generate test instructions for microprocessor RTL designs. The test instructions generated by MPFuzz can achieve higher coverage at least four times than that by the state-of-the-art fuzzing-based RTL test generation tool.

A rigorous approach to microprocessor verification using UVM

In today's fast-paced technology industry, microprocessors play an increasingly important role in a wide range of applications. However, verifying the correctness of complex microprocessor designs remains a significant challenge. To address this issue, a rigorous approach to microprocessor verification using the Universal Verification Methodology (UVM) is proposed. UVM provides a standardised and scalable approach to verifying digital designs, including microprocessors, and has been widely adopted in the industry. This research proposes a UVM-based verification framework for microprocessors that can identify and eliminate design errors early in the development cycle. The proposed approach covers functional verification, performance verification, and hardware-software co-verification. The effectiveness of the proposed approach is evaluated through a case study of a commercial microprocessor design, where the UVM-based verification framework successfully detected and resolved several design bugs. The results demonstrate the potential of the proposed rigorous approach to microprocessor verification using UVM to enhance the quality and reliability of microprocessor designs.

A Refinement-Based Approach to Spectre Invulnerability Verification

Several mitigations to thwart Spectre attacks have been proposed. However, design errors or trojans can be exploited to circumvent these mitigations. We have developed a highly-automated formal verification methodology that can detect if modern microprocessor designs are vulnerable to Spectre and its variants or prove otherwise. The methodology comprises of a refinement-based formal Spectre invulnerability property, and refinement maps, abstractions and invariants required to efficiently check the property. The methodology was evaluated on 29 benchmarks based on the RSD, which is an open source RISC-V based out-of-order superscalar processor. The benchmarks incorporated two Spectre defenses including software-controlled speculation and data track. Also incorporated were various implementation errors and hardware Trojans such as internally-triggered, rare-circuit-state and time-bombs that induce Spectre. What was evaluated was if the methodology could efficiently prove that an implementation is not vulnerable to Spectre and provide a counterexample otherwise. The methodology provided accurate classification for all benchmarks. The verification times were very efficient, ranging from 30 seconds to 1,500 seconds.

BTI-Aware Timing Reliability Improvement of Pulsed Flip-Flops in Nano-Scale CMOS Technology

Pulsed Flip-flops (FFs) are popular elements in the design of high-speed microprocessors. Technology scaling has led to a considerable increase in manufacturing process variation and aging phenomena affecting the reliability of these FFs. In this paper, the timing reliability of pulsed FFs is improved using a transistor-level restructuring technique. In this technique, we modify the pull-down network of pulsed FFs for decreasing the stress time (i.e., the time of being ON) of the pulsed clock transistors. Extensive Monte-Carlo based HSPICE simulations are conducted to show the effectiveness of the proposed restructuring technique under different process variation ratios and lifetime values. The obtained experimental result showed that the lifetime reliability of pulsed FFs is improved by 15% and at the expense of 4% area overhead under 30% process variation ratio and 9 years of operation time.

Survey on Microprocessor Agile Design Methodology and Technology

<p indent=0mm>The era of Dennard scaling and Moore’s law is coming to an end. As a result, it is more and more important to improve the performance of microprocessors through novel domain specific architectures. The growing complexity of domain specific architectures leads to a design productivity crisis, which stimulates the development of new tools and methodologies to enable the completion of complex chip designs on schedule and within budget for specific domain requirements. The global research practices gradually show that the microprocessor agile design methodology is an effective solution to the design productivity crisis. This survey first briefly discusses the essence of agile design methodology and the possibility of applying it to microprocessor design by comparing the characters between software and hardware designs. Then the paper reviews the main research work in recent years and shows the research status and development trends. Finally, we give some suggestions on the potential research directions for the near future.

A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder

A 4-bit Carry Look-Ahead (CLA) architecture for carry-generation process is proposed. CLA architecture proposed in this work uses complex CLA circuits for carry-generation rather than using carry-generate and carry-propagate functions which are used in the conventional process of 4-bit CLA architecture. Performance of the proposed CLA architecture is validated by performing simulation utilizing Cadence tools in standard 45 ​nm CMOS process. In order to prove effectiveness, performance of the proposed 4-bit CLA design is compared with existing 4-bit CLA designs. Moreover, as a possible application of the proposed design and to inspect performance in wide word length adder structure, the 4-bit CLA architectures (proposed and existing) are extended to 16-bits using Carry-Select Adder (CSA) architecture. Both as 4-bit cell and extended 16-bit structure, the proposed 4-bit CLA shows remarkable improvement in speed while maintaining quite acceptable level of power consumption. As a result, the proposed 4-bit CLA can be utilized as a highly suitable substitution of the existing 4-bit CLA architectures in high-speed microprocessor design.

Negative Capacitance Clock Distribution

In this paper, we investigate the ever-increasing power issue that is poised to jeopardize the performance and robustness of future low-power microprocessor design. We have observed a tremendous amount of research in low-power clock network design to bolster energy-efficient computing, without, however, any substantial improvement in overall microprocessor clock power and performance. In this work, we used the emerging ferroelectric negative capacitance field-effect transistor (NCFET) to reduce clock network effective capacitance and active elements, which enables low-power clocking. According to accurate HSPICE simulation, the proposed NCFET-based clocking can save up to 70 and 73 percent average power compared to the industry standard clocking schemes on industrial ISPD 2009 and ISPD 2010 benchmarks, respectively. In addition, the proposed methodology uses up to 20 percent fewer clock buffers compared to the existing synthesized clocking scheme and exhibits 49 percent lower crosstalk-induced delay variation compared to the traditional CMOS-based design.