Design Of Combinational Circuits Research Articles

Comparative performance evaluation of voltage gate-spin orbit torque MTJ-based digital logic circuits with 45 nm CMOS technology

The development of advanced logic systems relies on low-power, compact devices with incredibly fast computational speeds. Voltage gate spin–orbit Torque Magnetic Tunnel Junction has emerged as a prominent solution, meeting these requirements and playing a crucial role in the design of digital circuits. This paper concentrates on the design, implementation, and performance evaluation of gates (AND, OR, XOR) and combinational circuits (2 × 1 Mux, subtractor, and adder) based on VgSOT MTJ. The performance characteristics of these circuits have been evaluated, and comprehensive comparisons have been made with conventional 45 nm CMOS and SOT/STT-based circuit designs. In this paper, based on the latency performance analysis, it has been established that the logic gates and combinational circuits utilizing VgSOT exhibit superior performance of approximately 96% compared to CMOS counterparts. Similarly, latency performance improvement of 44% and 75%, respectively, is seen for VgSOT-based logic gates and combinational circuits over SOT and STT-based circuits. Analysis of power consumption in VgSOT-based logic gates has revealed a remarkable power efficiency of ∼98% over CMOS- and SOT/STT-based circuit implementations. Implementing VgSOT MTJ-based design brings about notable improvements in the performance of different logic designs.

Teaching Design and Practice of "Three-wide Education" Integrating into Combinational Logic Circuit Design

This article explores the integration of "Three-Wide Education" into the course ‘Digital Electronic Technology’ with a specific focus on the content related to the design of combined logic circuits. As education continues to evolve, the goals of higher education have shifted from simply imparting knowledge to nurturing students' holistic development and actively engaging them in societal progress. In today's social context, the cultivation of high-caliber electronic information professionals with a strong sense of social responsibility has become a central objective of higher education. Consequently, curriculum-based "Three-Wide Education" has gained prominence as a pivotal component of higher education reform. Drawing upon the thematic elements of "Three-Wide Education" within the chapter on combinatorial logic circuit design, this article embarks on instructional design. The primary objective is to seamlessly integrate knowledge dissemination with value-based guidance through practical exercises in "Three-Wide Education" within the curriculum.

Design of memristor-based combinational logic circuits

Design of memristor-based combinational logic circuits

A New Optimal Method for the Secure Design of Combinational Circuits against Hardware Trojans Using Interference Logic Locking

Effective resistance to intellectual property theft, reverse engineering, and hardware Trojan insertion in integrated circuit supply chains is increasingly essential, for which many solutions have been proposed. Accordingly, strong attacks are also designed in this field. One way to achieve the above goal is obfuscation. The hardware obfuscation method hides the primary function of the circuit and the normal Netlist from the attacker by adding several key gates in the original Netlist. The functionality circuit is correct only if the correct key is applied; otherwise, the circuit is obfuscated. In recent years, various obfuscation methods have been proposed. One is logic locking, the most prominent hardware protection technique since it can protect against untrusted items. Logic locking induces functional and structural changes to a design even before the layout generation. We secured the circuit against hardware Trojan insertion with a secure logic locking method based on the insertion of key gates in interference mode. We call our proposed method Secure Interference Logic Locking, SILL. SILL is based on minimum controllability in paths with maximum fan-out. In this method, we have reduced the number of key gates required for circuit obfuscation and created the maximum Hamming distance between normal and obscure outputs. In addition, the key gates are added to the circuit’s complete interference, and the AES algorithm is used to generate the key. Our proposed method, SILL, was simulated in the Vivado simulation environment; the algorithms used in this method were prepared in VHDL language and designed to allow parallel execution, then applied on the original Netlist of the ISCAS85 benchmark circuits. By analyzing and comparing the results of this simulation to recent works, the amount of hardware consumption has decreased (about 5% space consumption and about a 0.15-nanosecond time delay). Then, the SAT attack algorithm was tested on ISCAS85 benchmark circuits that were obfuscated with SILL. The execution time of the attack in the second attempt was 0.24 nanoseconds longer compared to similar recent works, and it timed out in the fourth attempt. The resistance of our proposed method, having less hardware overhead and higher speed is more effective against SAT attacks than the existing conventional methods.

Design of Optical Combinational Circuits Utilized with Hybrid Plasmonic Waveguides

Design of Optical Combinational Circuits Utilized with Hybrid Plasmonic Waveguides

Hardware-Efficient Approximate Dividers for Image Processing in WSN Edge Devices

This paper proposes a hardware-efficient implementation of division, which is useful for image processing in WSN edge devices. For error-resilient applications such as image processing, accurate calculations can be unnecessary overhead, and approximate computing that obtains circuit benefits from inaccurate calculations is effective. Since there are studies showing sufficient performance with few bit operations, this paper proposes a combinational arithmetic circuit design of 16 bits or less. The proposed design is an approximate restoring division circuit implemented with a 2-dimensional array of 1-bit subtractor cells. The main drawback of such a design is the long “borrow-chain” that traverses all of the rows of the 2-dimensional subtractor array before a final stable quotient result can be produced, thereby resulting in a long delay and excessive power dissipation. This paper proposes two approximate subtractor cell designs, named ABSC and ADSC, that break this borrow chain: the first in the vertical direction and the second in the horizontal direction, respectively. The proposed approximate divider designs are compared with an accurate design and previous state-of-the-art designs based on accuracy and hardware overhead. The proposed designs have accuracy levels that are close to the best accuracy levels achieved by previous state-of-the-art approximate divider designs. In addition, the proposed ADSC design had the lowest delay, area, and power characteristics. Finally, the implementation of both proposed designs for two practical applications showed that both designs provide sufficient division accuracy.

Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology

Quantum-dot cellular automata (QCA), due to its unique characteristics like low power consumption, nanoscale design, and high computing speed is considered as an emerging technology, and it can be used as an alternative for CMOS technology in circuit design for quantum computers in the near future. XOR gate has many applications in the design of digital circuits in QCA. In this paper, an efficient novel structure of XOR gate is proposed in QCA. Also, a novel 1-bit comparator circuit, 1-bit full adder, binary to gray and gray to binary convertor code based on the proposed XOR is designed and simulated using QCADesigner 2.0.3. The simulation results demonstrated that the proposed structures provide improvements compared to previous works in terms of QCA cells count, area, and circuit cost.

Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design

Cartesian genetic programming (CGP) represents the most efficient method for the evolution of digital circuits. Despite many successful applications, however, CGP suffers from limited scalability, especially when used for evolutionary circuit design, i.e. design of circuits from a randomly initialized population. Considering the multiplier design problem, for example, the 5\(\times\)5-bit multiplier represents the most complex circuit designed by the evolution from scratch. The efficiency of CGP highly depends on the performance of the point mutation operator, however, this operator is purely stochastic. This contrasts with the recent developments in genetic programming (GP), where advanced informed approaches such as semantic-aware operators are incorporated to improve the search space exploration capability of GP. In this paper, we propose a semantically-oriented mutation operator (\(\mathrm {SOMO}^k\)) suitable for the evolutionary design of combinational circuits. In contrast to standard point mutation modifying the values of the mutated genes randomly, the proposed operator uses semantics to determine the best value for each mutated gene. Compared to the common CGP and its variants, the proposed method converges on common Boolean benchmarks substantially faster while keeping the phenotype size relatively small. The successfully evolved instances presented in this paper include 10-bit parity, 10 + 10-bit adder and 5\(\times\)5-bit multiplier. The most complex circuits were evolved in less than one hour with a single-thread implementation running on a common CPU.

Design and comparative analysis of memristor-based transistor-less combinational logic circuits

ABSTRACT Memristor-based combinational logic is one of the unique concepts of designing digital circuits to achieve compact design, faster operation, and lesser power consumption. This work presents a unique memristor-based transistor-less combinational logic circuits design and analyses the performance benchmarking with other state of the art methods. Observed results demonstrated that the proposed design performs comparatively well in terms of size, speed, and power consumption. Basic combinational logic circuits, such as full adder, multiplexer, decoder, and priority encoder are being designed using the University of Michigan Model. The basic logic gates which include AND, OR, XOR are also designed using the concept of memristor ratioed logic. The proposed design of full adder utilises 14 memristors and 2 inverters, the delay time is 26.5ps, and power consumption is 0.5nW which is less compared to the other design. The proposed 4 × 1 multiplexer, 2-to-4 decoder and 4-to-2 priority encoder consume 0.6nW, 0.15nW, and 0.87nW power respectively. The observed improvement in these significant parameters demonstrates the potential of using memristor-based transistor-less combinational logic circuits in modern electronic devices.

Design of Arithmetic Logic Unit using Pseudo Dynamic Buffer based Domino Logic

Design of combinational circuits using dynamic logic has the advantage of high speed and less area when compared to conventional CMOS logic. However, it pose problem while cascading dynamic logic architectures and also more prone to leakage current issue. These issues are overcome by using domino logic with static inverter at the output of dynamic node. The increased power dissipation at the output node is reduced by using pseudo dynamic buffer based domino logic by having static like switching at the output node. This paper details the design of arithmetic and logic unit designed using conventional and pseudo dynamic buffer based domino logic. The arithmetic unit comprise adder, subtractor, multiplier and logical unit comprise AND, NAND, OR, NOR and XOR logic blocks based on pseudo dynamic buffer based domino logic and it is compared with the Arithmetic logic unit designed using conventional domino logic. The design and simulations are performed using UMC90nm technology node library using Cadence® Virtuoso® tool. The simulation result of ALU unit demonstrates that arithmetic logic unit designed using PDB logic has reduction in power consumption by 89.14% and delay by 1.995% while compared to conventional domino logic.

Full Adder Circuit Design with Novel Lower Complexity XOR Gate in QCA Technology

Quantum-dot Cellular Automata (QCA) is a new technology for designing digital circuits in Nanoscale. This technology utilizes quantum dots rather than diodes and transistors. QCA supplies a new computation platform, where binary data can be represented by polarized cells, which can define by the electron’s configurations inside the cell. This paper explains QCA based combinational circuit design; such as half-adder and full-adder, by only one uniform layer of cells. The proposed design is accomplished using a novel XOR gate. The proposed XOR gate has a 50% speed improvement and 35% reduction in the number of cells needed over the best reported XOR. The results of QCADesigner software show that the proposed designs have less complexity and less power consumption than previous designs.

Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme

Due to the reduction in device feature size and supply voltage, achieving soft error reliability in sub-micrometer digital circuits is becoming extremely challenging. We consider the problem of choosing the gate sizes in a combinational logic circuit in order to minimize the soft error rate (SER) of the circuit. This problem can be solved using the heuristic as well as the greedy-based approaches for small-size problems; however, when the circuit size increases, the computational time grows exponentially, and hence, the previous methods become impractical. This paper proposes a novel technique for soft error tolerant design of large-scale combinational circuits using a cone-oriented gate sizing. Circuit partitioning is used to split the circuit into a set of small sub-circuits. The gates of sub-circuits are resized, such that the entire circuit SER is reduced based on a new soft error descriptor metric. The proposed cone-oriented gate sizing framework is used for selective gate sizing, leading up to 31% SER reduction with less than 17% area overhead when applied to large-scale benchmarks. The results also show that the proposed method is 21% more efficient and up to 292 times faster when compared with that obtained using a similar work based on the sensitive-based gate sizing scheme.

Analysis Of Low Power And Reliable XOR-XNOR Circuit For High Speed Applications

This paper presents a comprehensive study of different types of XOR-XNOR circuits. Our main focus is to characterise the XOR-XNOR combinational circuit design using six transistors for low power applications. The six transistor XOR-XNOR circuit can be simulated using 45nm CMOS technology in cadence virtuoso using foundry files. The simulation results demonstrates, parameters such as power, delay and power delay product(PDP) at different voltages ranging from 0.4 to 1v respectively. From the obtained results it clearly indicates the proposed design has low power consumption and full voltage swing.

Design and Analysis of Memristor-based Combinational Circuits

ABSTRACTThis paper presents a novel memristor-based combinational circuit, namely: 4:2 priority encoders, 2:4 decoder, and BCD to EX-3 code converter. The performance of all these logic circuits is analyzed with respect to equivalent CMOS. The proposed work extends the philosophy of designing gate level circuit and then using the basic gate design to implement the combinational circuit. Memristor gates are used to implement the desired logic function. In the proposed work, memristor-based novel XOR gate is designed. This gate is then utilized to implement the encoder, decoder, and BCD to EX-3 code converter circuits. The proposed circuits have the advantage like low transistor count, high speed, and low power. The simulation is carried out in LTSPICE.

A Fast and Self-Repairing Genetic Programming Designer for Logic Circuits

Usually, important parameters in the design and implementation of combinational logic circuits are the number of gates, transistors, and the levels used in the design of the circuit. In this regard, various evolutionary paradigms with different competency have recently been introduced. However, while being advantageous, evolutionary paradigms also have some limitations including: a) lack of confidence in reaching at the correct answer, b) long convergence time, and c) restriction on the tests performed with higher number of input variables. In this paper, we have implemented a genetic programming approach that given a Boolean function, outputs its equivalent circuit such that the truth table is covered and the minimum number of gates (and to some extent transistors and levels) are used. Furthermore, our implementation improves the aforementioned limitations by: Incorporating a self-repairing feature (improving limitation a); Efficient use of the conceivable coding space of the problem, which virtually brings about a kind of parallelism and improves the convergence time (improving limitation b). Moreover, we have applied our method to solve Boolean functions with higher number of inputs (improving limitation c). These issues are verified through multiple tests and the results are reported.

A Self-Repairing Digital System with High-Quality Scalability and Fault Coverage

In any fault tolerant or BIST system the primary goal is to covenant with faults that arise in the indented system. The proposed system using genetic algorithm to optimize the performance and area of given circuit. This approach is supple for combinational circuit design. The use of four spare cells simplifies the operation of the active block in the current system; it needs more space to establish itself so it is considered as overhead. The proposed method of fault detection and correction for logical errors using genetic algorithm decreases the area overhead. Detection of Fault in the memory unit through BIST implementation increases the speed but replacing the existing faulty block with fault free block degrades the fault analyzing capabilities. Utmost care has on all the works implemented for the process of minimizing the error in different digital process. Therefore, with the new scope of proposing the method of reducing the error flow for the application of medical field, aeronautical, satellite broadcasting is described very efficiently in this paper. The simulation results of the fault tolerant and self-repairing method using genetic algorithm is presented.

Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design

Pulse width of single event transient can be shrunk by pulse quenching effect in combinational circuits. And it is found that the pulse quenching effect is closely related to the layout of the circuits. In this paper, we propose a placement method for reducing soft errors in combinational circuits by increasing the number of quenching unit and enhancing the pulse quenching effect between them. To evaluate the soft error automatically, an evaluation platform is also implemented and embedded into commercial EDA tools with our placer. Simulation results show that our proposed method can reduce the soft error vulnerabilities by 14%–26%.

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.

Implementation and Analysis of Methods for Error Detection and Correction on FPGA

In this paper, two methods are implemented and analyzed on a Field Programable Gate Array (FPGA) board for the design of fault-tolerant pipelined sequential and combinational circuits. Evaluated methods are named Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC). The mentioned methods are based on Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant master-slave flip-flops with fault tolerant memory elements. Additional to the analysis and implementation of the methods, the enhancement to a method is proposed.

Study and Performance Analysis of MOS Technology and Nanocomputing QCA

One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.