Implementation and Analysis of Methods for Error Detection and Correction on FPGA

Abstract

In this paper, two methods are implemented and analyzed on a Field Programable Gate Array (FPGA) board for the design of fault-tolerant pipelined sequential and combinational circuits. Evaluated methods are named Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC). The mentioned methods are based on Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant master-slave flip-flops with fault tolerant memory elements. Additional to the analysis and implementation of the methods, the enhancement to a method is proposed.