Analog Circuit Design Research Articles

Comparative analysis of meta heuristics algorithm for differential amplifier design

The design of analog circuits is very essential for the development of system design based on electronics as the world is analog in nature. Furthermore, performance of emerging products depends on analog circuits for reduction of power dissipation and improvement of speed. Though in the system on chip (SoC) analog circuit consumes less, it is more complex to design it due to the analog circuit nature complexity. The job of the evolutionary algorithm (EA) in the process of optimization of an analog circuit based on complementary metal oxide semiconductor (CMOS) is to get the appropriate values that can be used for the design parameters of the given circuit in such a way such that all the targeted specification of the given circuit can be obtained. The chaotic serial particle swarm optimization (CSPSO) and cuckoo search (CS) algorithms are lower than to those found through the particle swarm optimization (PSO) and differential evolution (DE) algorithms. The CS algorithm obtained all the desired specifications with less power dissipation and the least total transistor area compared to those attained by the DE and PSO algorithms.

A near‐DC measurement and modelling of low‐frequency noise in electronic components

AbstractLow‐frequency noise, generated inherently by the number or mobility fluctuation of carriers, is a crucial concern for the design of analog and digital circuits. Unified modelling based on experimental validation of near‐DC noise in amplifiers is a long‐standing open problem. This article develops a model for low‐frequency noise by deriving new bounds for carrier capturing and releasing. According to the proposed model, a measurement system is suggested that operates in a wide frequency range and even at very low frequencies. The system is noise‐tolerant, since the amplifier is selected based on acceptable noise levels. Among the advantages are the independence from specialized structural noise models for each component and the low cost of the measurement system. The evaluation results show that the proposed method leads to a promising improvement in the low‐frequency noise measuring and is superior to conventional models in the normalized root mean square error indicator. Findings reveal that the proposed measurement method can estimate the flicker noise around the DC frequency, and the proposed model agrees reasonably with the proposed measurement circuit.

Implementation And Comparison of Different Stages of Current Starved CMOS Ring Oscillator – A Study

The ring oscillators serves as the fundamental building blocks in both digital and analog circuit design, as its extensive use is found in various electrical systems, including phase-locked loops, frequency dividers, and clock generators. This study gives a general overview of the ring oscillator circuit, including its workings, uses, and important design considerations. The ring oscillator generates timing signals for synchronous operation and is often employed as a clock generator in digital systems. It may also be used as a frequency divider to separate higher frequencies into lower ones. A closed loop is used to connect an odd number of inverting stages to create the ring oscillator circuit. An inverter, which is often built using complementary metal-oxide-semiconductor (CMOS) technology, is a component of every stage. By adding a delay to each step, the ring oscillator creates a self-sustaining oscillation. The development and comparison of 3, 5, and 7 stage ring oscillators for different performance metrics, as well as corner analysis for propagation delay and the effect of temperature on the operation of the ring oscillator was performed using Cadence Virtuoso with 90nm technology. This comparison of several phases of a current-starved (CS) ring oscillator offers an advantage to the best design with innovation based on the technology employed and outcomes from the corner analysis, which hasn't been done in any of the more recent researches.

Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective

This work incorporates an in-depth physics-based investigation of Nanosheet FET’s (NSFET’s) extension region for analog circuit design. When extension length (LEXT) is changed from 8 nm to 3 nm, the NSFET exhibits an increment in IOFF (∼8×) and subthreshold swing ‘SS’ (∼5mV/dec), with a ∼1.5× enhancement in ION. Though driving capacity does not increase proportionally on stacking the sheets owing to the location of contacts, however the ION/IOFF ratio increases by ∼ 10× on stacking two more sheets. A common source (CS) amplifier is utilized for the analysis of the circuit-level performance. The gain-bandwidth profile is worth highlighting that the extension region gives feasibility to modulate the gain and bandwidth of the amplifier as compared to sheet stacking. It is investigated that a higher extension length (8 nm) gives a ∼27% higher gain, while a lower LEXT (3 nm) gives ∼2× higher bandwidth. Though sheet stacking increases the ON current, it does not significantly impact the gain, bandwidth, or phase shift.

A Novel Framework of Genetic Algorithm and Spectre to Optimize Delay and Power Consumption in Designing Dynamic Comparators

In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effective in finding near-optimal solutions, it has not been extensively applied to the field of analog circuit design. Hence, this paper proposes a method to utilize GA in the optimization of a widely used circuit topology, namely the comparator. The comparator is considered the fundamental block in the design of most analog-to-digital converters (ADCs). For high-speed ADCs, dynamic comparators are usually chosen for the purpose of high speed and power efficiency. In summary, this paper introduces an innovative GA-Spectre architecture to optimize the dynamic comparator with respect to delay and power consumption. The post-optimized results are optimistic with a 72.61 ps delay and 3.11 µW power dissipation.

Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

This work presents an experimental evaluation of n-type, gate-all-around (GAA), vertically stacked nanosheet field effect transistors (NSFETs) operating in a temperature (T) range from 473 K down to 173 K and focusing on their use for analog applications. Devices with gate lengths (Lgate) of 28 nm to 200 nm were analyzed. Besides exhibiting a slight short channel effect, the shorter transistors show a good performance in terms of analog application, presenting at 173 K an intrinsic voltage gain (AV) of 30 dB and unit gain frequency (fT) of 185 GHz. This is also seen in two figures of merit that characterize the transistor performance for analog circuit design: the transistor efficiency (gm/IDS) and the gain frequency product (AV*fT). The optimum region of operation was demonstrated to be at strong inversion by the trade-off between gm/IDS and fT, where in this region Lgate = 28 nm presents a gain frequency product of ∼ 5,5THz at T = 173 K. At lower temperature, as expected, it is confirmed that the carrier mobility and the subthreshold swing (SS) improve while the threshold voltage (VT) increases.

A Revolution In Design

Agile Analog is helping to revolutionise the design of analogue and mixed-signal circuits.

Pretraining Graph Neural Networks for Few-Shot Analog Circuit Modeling and Design

Being able to predict the performance of circuits without running expensive simulations is a desired capability that can catalyze automated design. In this paper, we present a supervised pretraining approach to learn circuit representations that can be adapted to new circuit topologies or unseen prediction tasks. We hypothesize that if we train a neural network (NN) that can predict the output direct current (DC) voltages of a wide range of circuit instances it will be forced to learn generalizable knowledge about the role of each circuit element and how they interact with each other. The dataset for this supervised learning objective can be easily collected at scale since the required DC simulation to get ground truth labels is relatively cheap. This representation would then be helpful for few-shot generalization to unseen circuit metrics that require more time consuming simulations for obtaining the ground-truth labels. To cope with the variable topological structure of different circuits we describe each circuit as a graph and use graph neural networks (GNNs) to learn node embeddings. We show that pretraining GNNs on prediction of output node voltages can encourage learning representations that can be adapted to new unseen topologies or prediction of new circuit level properties with up to 10x more sample efficiency compared to a randomly initialized model. We further show that we can improve sample efficiency of prior SoTA model-based optimization methods by 2x (almost as good as using an oracle model) via fintuning pretrained GNNs as the feature extractor of the learned models.

Noise-Aware FET Circuit Design Based on C/ID-Invariant

This article presents an analytical approach, supported by experimental data, to design analog circuits for given noise and speed specifications. As an extension to traditional design methodologies, i.e., Inversion Coefficient (IC) and gm/ID (GmID), the proposed approach aims to gain more in-depth insight, while providing appropriate analytical means for circuit design, at lower levels of computing complexity. Based on a recently proposed design approach, the C/ID method relies on device characteristic capacitance, i.e., CS = CS/ID as an invariant, where CS refers to the Field-Effect Transistor (FET) device self-loading capacitance. C/ID provides the opportunity to derive closed-form solutions to some key design optimization problems such as power versus Gain Bandwidth (GBW) and noise trade-offs. Examples for common-source amplifiers and Ring Oscillators (RO) have been provided. A set of current-steering ROs has been designed and fabricated in 0.18 lm technology based on the proposed flow. The circuit Phase Noise (PN) was characterized and compared to the predictions of the proposed design methodology, demonstrating favorable matching.

Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial Intelligence

While Moore's law has driven exponential computing power expectations, its nearing end calls for new avenues for improving the overall system performance. One of these avenues is the exploration of alternative brain-inspired computing architectures that aim at achieving the flexibility and computational efficiency of biological neural processing systems. Within this context, neuromorphic engineering represents a paradigm shift in computing based on the implementation of spiking neural network architectures in which processing and memory are tightly co-located. In this paper, we provide a comprehensive overview of the field, highlighting the different levels of granularity at which this paradigm shift is realized and comparing design approaches that focus on replicating natural intelligence (bottom-up) versus those that aim at solving practical artificial intelligence applications (top-down). First, we present the analog, mixed-signal and digital circuit design styles, identifying the boundary between processing and memory through time multiplexing, in-memory computation, and novel devices. Then, we highlight the key tradeoffs for each of the bottom-up and top-down design approaches, survey their silicon implementations, and carry out detailed comparative analyses to extract design guidelines. Finally, we identify necessary synergies and missing elements required to achieve a competitive advantage for neuromorphic systems over conventional machine-learning accelerators in edge computing applications, and outline the key ingredients for a framework toward neuromorphic intelligence.

СХЕМОТЕХНИЧЕСКИЕ МЕТОДЫ ПОВЫШЕНИЯ БЫСТРОДЕЙСТВИЯ ОПЕРАЦИОННЫХ УСИЛИТЕЛЕЙ НА ОСНОВЕ «ПЕРЕГНУТОГО» КАСКОДА

Three circuit techniques are proposed that provide (with simultaneous use) an increase bymore than two orders of magnitude of the maximum output voltage slew rate (SR) of microelectronicoperational amplifiers (op-amps) based on bipolar transistors with a classical architecture,designed to operate in automatic control systems, radio engineering and communications, forexample, as drivers for ultra-high-speed analog-to-digital converters (EVIOAS150, EVIOAS350,AD9208, AD9691, 1273PV14, etc.). The considered op-amps contain a cascode input stage with anon-linear correction of the pass-through characteristic and a tracking circuit that increases theattenuation coefficient of the input common-mode signals and the noise suppression coefficient onthe power buses, as well as an intermediate stage based on a “folded” cascode. The use of a"folded" cascode makes it possible to increase the efficiency of using power supply voltages, aswell as to increase the unity gain frequency of the corrected op-amp. However, such an intermediatestage is an essential non-linear link that limits the maximum output currents that recharge theop-amp correction capacitor. The results of computer simulation of two modifications of theAmpSR1, AmpSR2 op amps, which differ from each other in the structure of a nonlinear parallelchannel, which eliminates the dynamic overload of a "folded" cascode, are presented. The relevanceof the research performed is related to the problems of import substitution in the class ofhigh-speed op-amps and the lack of new and promising ideas for increasing the SR of the op-ampbased on the simultaneous use of non-linear and differentiating transient correction circuits in thelarge signal mode among analog circuit designers. The considered circuit techniques are alsoeffective when using CMOS technological processes.

A unified black‐box macro model for analog circuit based on artificial neural network

SummaryA novel unified black‐box macro model for analog circuits is presented. This black‐box macro model enables the creation of a high‐accuracy DC and AC macro model by modeling the port voltages and currents of analog circuits using an artificial neural network (ANN). The modeling process for different analog circuit blocks is the same, as the model can be modeled by extracting only the port values. The operational amplifier (OPAMP), which is an important module of the analog circuit, is taken as an example for the verification of the model proposed in this work. The black‐box macro model of OPAMP is used for DC, AC, and transient simulations. The simulation speed of the black‐box macro model is much better than that of the transistor‐level model, and the trade‐off between accuracy and speed can be freely adjusted. The black‐box macro model of OPAMP is also validated by bandgap and low dropout regulators (LDO). To verify the accuracy of the model, the experimental measurement results of the LDO circuit fabricated in the 0.18 μm process have been obtained. Compared with the measurement results, the simulation results of both transistor and black‐box macro models have high accuracy. Those results demonstrate the great potential of the black‐box macro model in analog circuit design and simulation.

A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology

Despite the scaling of the supply voltage of deep-submicrometer CMOS technologies, many applications still require to deal with off-chip signals in high-voltage domains (e.g., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.3$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5~ \mathrm{V})$</tex-math> </inline-formula> . Hence, foundries offer fabrication processes with voltage-tolerant transistors, which are inherently protected from the electrical stress, at the expenses of compromising their performances, reducing the design portability, and augmenting the production costs in case of the customization of the process. As an alternative, circuit techniques, such as cascoding, adaptive biasing, and voltage shifting, result effective in designing analog circuits, such as amplifiers and voltage drivers at high supply voltage with voltage-scaled transistors. This article presents the architecture of a switch for analog multiplexers (MUXs) able to handle signals up to twice the nominal supply voltage of the employed transistors. To validate the circuit choice, a switch for a 5-V MUX has been designed with 2.5-V transistors in 28-nm CMOS technology. The comparison with a benchmark architecture with tailored 5-V devices shows that an about three times larger area and 4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> A static current demand have to be considered. Moreover, an accelerated degradation test (ADT) showed a similar decay of the features of both types of switches.

A Memristive-Based Design of a Core Digital Circuit for Elliptic Curve Cryptography

The new emerging non-volatile memory (NVM) devices known as memristors could be the promising candidate for future digital architecture, owing to their nanoscale size and its ability to integrate with the existing CMOS technology. The device has involved in various applications from memory design to analog and digital circuit design. In this paper, a combination of memristor devices and CMOS transistors is working together to form a hybrid CMOS-memristor circuit for XAX- Module, a core element used as digital circuit for elliptic curve cryptography. The proposed design was implemented using Pt/TaOx/Ta memristor device and simulated in Cadence Virtuoso. The simulation results demonstrate the design functionality. The proposed module appears to be efficient in terms of layout area, delay and power consumption since the design utilizes the hybrid CMOS/memristor gates.

On Reducing LDE Variations in Modern Analog Placement

Layout-dependent (LDEs) introduce an inevitable performance degradation in analog and mixed-signal circuit design with advanced process technologies below 90 nm. The main LDE sources, including the well proximity effect (WPE), length of diffusion (LOD), and the oxide-to-oxide spacing effect (OSE), cause substantial fluctuations in carrier mobility and threshold voltage of transistors. In traditional design flows, impact of these in post-layout simulation, leading to expensive re-design iterations by inspecting the physical locations of devices with respect to one another. In this article, we introduce the concept of an ideal mobility multiplier based on physics models, in order to minimize the LDE effects with a fast simulated annealing algorithm through various LDE alleviating operations. Based on the introduced mobility multiplier and the hierarchical B*-tree (HB*-tree) topological representation, our LDE-aware analog placement methodology can simultaneously optimize not only the area and wire length, but also the LDEs, while maintaining linear-packing time complexity of HB*-trees. Compared to the most recent works on 65 nm-based analog circuits, experimental results show that the proposed method can effectively and efficiently reduce LDE variations, while improving the circuit performance.

Analytical drain current model development of twin gate TFET in subthreshold and super threshold regions

In this work, an analytical model for a twin gate Tunnel Field Effect Transistor's drain current operating in the subthreshold and superthreshold regions is proposed. Using this drain current model, the ratio of transconductance to drain current, a crucial metric for the integrated analog circuit design technique, has been retrieved. Due to the simplicity of this approach, it may be quickly implemented for any type of dual gate TFETs by adjusting a few parameters. Comparing the drain current calculated by this analytical model to the drain current simulated by the 2D-Sentaurus TCAD software demonstrates the Tunnel FET's authenticity. The proposed analytical method can be used to achieve the appropriate transconductance for operating Tunnel FETs in the gigahertz region with very low milliwatt power consumption.

M-Polar Fuzzy Graphs and Deep Learning for the Design of Analog Amplifiers

The design of analog circuits is a complex and repetitive process aimed at finding the best design variant. It is characterized by uncertainty and multivariate approaches. The designer has to make different choices to satisfy a predefined specification with required parameters. This paper proposes a method for facilitating the design of analog amplifiers based on m-polar fuzzy graphs theory and deep learning. M-polar fuzzy graphs are used because of their flexibility and the possibility to model different real-life multi-attribute problems. Deep learning is applied to solve a regression task and to predict the membership functions of the m-polar fuzzy graph vertices (the solutions), taking on the role of domain experts. The performance of the learner is high since the obtained errors are very small: Root Mean Squared Error is from 0.0032 to 0.0187, Absolute Error is from 0.022 to 0.098 and Relative Error is between 0.27% and 1.57%. The proposed method is verified through the design of three amplifiers: summing amplifier, subtracting amplifier, and summing/subtracting amplifier. The method can be used for improving the design process of electronic circuits with the possibility of automating some tasks.

Performance analysis of CMOS based analog circuit design with PVR variation

Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), particle swam optimization (PSO), hybrid CSPSO, and differential evaluation (DE) algorithms is presented. Each algorithm is implemented using the C programming language, interfaced with Ngspice circuit simulator, and tested on the Intel®core™ i5, 2.40 GHz processor with 8 GB internal RAM using the Ubuntu operating system (OS). The result shows PVT variation affects the performance of CMOS circuit.

A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling

Device sizing is a challenging problem for analog circuit design. Traditional methods depend on domain knowledge and intensive simulations to search for feasible parameters. Recent studies apply the Bayesian optimization (BO) and a Gaussian process (GP) model in analog circuit synthesis to improve efficiency. The BO framework automatically selects the parameter candidates by inferring the surrogate GP model. However, naive BO employs a sequential updating strategy which is inefficient in a multicore environment. Besides, the widely used GP model requires costly high fidelity data, which are obtained from fine simulations. In this article, we propose a constrained batch BO approach with a multifidelity (MF) model to solve the above difficulties. The batch BO exploits parallel computing and selects promising parameters by multiple acquisition function ensemble. In addition, the MF GP model adapts the low fidelity data obtained from coarse simulations. Specifically, the proposed method incorporates information gain in a weighted clustering algorithm to refine the parameter candidates. As a result, the proposed method maintains the candidates’ quality and diversity, which speeds up the optimization convergence. In the experiments, we demonstrate the efficiency of the proposed approach on three real-world circuits. The results show that our approach reduces the simulation costs by at least 54.6% compared to the state-of-the-art baselines.

Radiation-aware analog circuit design via fully-automated simulation environment

As a result of increased interest in space applications, radiation-aware circuit design has become a major concern to guarantee the safe operation of electronic systems operating under extreme space conditions. As the first step, several ad-hoc simulation approaches have been developed in analog and digital domains to estimate the functional behavior of circuits exposed to high radiation. However, most of these tools are application specific and stand-alone (not integrated into the simulation tools). Also, several commercial CAD solutions exist; however, access to these tools is limited due to security measures. To this end, we have developed a well-equipped, SPICE-integrated, and free-to-access simulation tool, RadiSPICE, capable of running statistical radiation simulations and performing extended temperature and sensitivity analyses. By using RadiSPICE, one can readily predict the functional behavior of circuits after long-term or short-term radiation effects. Moreover, the sensitivity analysis reveals vulnerabilities of the design against radiation and provides valuable design hints to the designer to make circuits radiation-hardened. To demonstrate the proposed tool, we have performed several experiments on two analog building blocks with different topologies (bandgap reference and comparator circuits) using RadiSPICE and discussed the robustness of the designs in detail.